Infineon OPTIREG TLF30681QVS01, Руководство пользователя

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Table 26 Event response mapping – other events (continued)
Event Move to
FAULT Move to
ACTIVE;
Generate
RESET
Move to
DISABLED No transition;
Generate
interrupt
Buck2: OT warning – – – X
Buck2: OT fault X – – –
Monitoring: OT warning – – – X
Monitoring: OT fault X – – –
Figure 22 shows the timing of soft reset generation and hard reset generation after an initialization error.
t
t
Reset events
POR
HIGH
LOW
FSM State
t
Device enters Fault state after second
initialisation error (hard reset event
à all
regulator off)
Stat All Regs
ON
OFF
t
All regulators are switched on
ROT
Start INIT timer
no SPI Com or no WD response is
detected before second Initialisation
time is expired
HIGH
Stat communication
POR FAULT ACTIVE
Start up with first Initialisation Error Start up with second Initialisation Error
Second INIT error detected, Hard
Reset event is generated & FSM
moved to Fault state
t
POR
HIGH
LOW
Device remains in Active state after first initialation error
Stat All Regs
ON
OFF
t
All regulators are switched on
ROT
HIGH
LOW
Start INIT timer
Stat communication
Initialisation time window
no SPI Com or no WD response is detected before
Initialisation time is expired, First INIT error detected,
Soft Reset is trigger
Reset delay time
t
POR ACTIVE
t
t
FSM State
Initialisation time window
HIGH
LOW
Start INIT timer
Initialisation time window Reset delay time
t
Initialisation time window
Reset events
t
Figure 22 Reset generation timing
Figure 23 shows the reset counter and the transition to LOCKED mode after three initializations failure.
OPTIREG
™
PMIC TLF30681QVS01
Power management IC
State machine
Datasheet 83 Rev. 1.0
2020-04-08