User’s Manual
6-1
05.99
On-Chip Peripheral Components
C513AO
6
On-Chip Peripheral Components
6.1
Parallel I/O
The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2,
and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as
inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will
float when configured as input.
The output drivers of Port 0 and Port 2 and the input buffers of Port 0 are also used for accessing
external memory. In this application, Port 0 outputs the low byte of the external memory address,
time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external
memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the
P2 SFR contents. In this case, Port 0 is not an open-drain port, but uses a strong internal pull-up
Field Effect Transistors (FETs).
Port 1 pins used for Synchronous Serial Channel (SSC) outputs are true push-pull outputs. When
used as SSC inputs, they float (no pull-up).
6.1.1 Port Structures
Each port bit consists of a latch, an output driver(s), and an input buffer. Read and write accesses
to the I/O Ports P0, P1, P2, and P3 are performed via the corresponding Special Function Registers.
Figure 6-1 shows a functional diagram of a typical latch and I/O buffer, which is the core of each of
the four I/O ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which
will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. Both
the output of the latch and the actual state of the port pins can be read, depending on the instruction
used for accessing the port.
Figure 6-1
Basic Structure of Port Circuitry
