
AURIX
™ lite Kit V2
Hardware Description
Board Users Manual
7
Revision October, 2020
1.1
Block Diagram
The block diagram in Figure 1 shows the main components of the AURIX
™ lite Kit V2 and their
interconnections.
Figure 1
Block Diagram of the AURIX
™ lite Kit V2
Aurix
ä
TC375, TC365,
TC275 or TC265
Micro
USB2.0
UTMI
PHY
EEPROM
Interface
FTDI
FT2232HL
EEPROM 1kB
93LC46B-I/SN
Octal Bus
Buf fer Gate
2 x Single-Bit
Bus Tranceiver
Single Bus
Buf fer Gate
MPSSE
Channel
A
OCDS
DAP
Connector
Ext. Oscillator
Input
2x LEDs
for OCDS
Power
LDO
Power
Interface
Ext. Power
Input
Pin Header X1
2x20, 0.1"
Pin Header X2
2x20, 0.1"
Arduino
ä
Pin Header (DIGITAL)
Arduino
ä
Pin Header (ANALOG IN)
ADC
GPIO
L
E
D
1
/L
E
D
2
B
u
tt
o
n
1
R
e
se
t
B
u
tt
o
n
3.3V
VDD
R35/0R
Ext.
Gate
Ctrl
Dig. Core
Supply
VDD
Ext. Osci
Input
20 MHz
External
Crystal
Port 11, 13,
14, 15, 20,
21, 22, 23
P00.5/
P00.6
PORSTN
Port
32,33
Port 0
Infineon
CAN Tranceiver
TLE9251VSJ
12 MHz
External
Crystal
CAN0
Node0
CAN Header
1x2, 0.1"
Q
S
P
I1
I2
C
0
A
S
C
L
IN
M
ikr
o
bu
s
ä
C
o
n
n
e
ct
o
r
S
h
ie
ld2
G
O
S
lo
t1
S
2
G
2
I2C0
ASCLIN1
QSPI2
I2C0
ASCLIN3
QSPI0
UART
S
h
ie
ld2
G
O
S
lo
t1
S
2
G
1
I2C0
ASCLIN2
QSPI0
UART
UART
ADC/AN26
ADC/AN16
ADC/AN17
ADC/AN19
ADC/AN18
GPIO
GPIO
GPIO
3.3V
A
N
3
6
-3
9
A
S
C
L
IN
0
I2
C
0
G
P
IO
Q
S
P
I1
EEPROM 2kB
24AA02E48-E/OT
EUI-48
ä
Node Address
A
N
2
4
-2
5
Ethernet Phy
DP83825IRMQR
RJ45
Power
LDO
DC IN
C39/22µF
L3/3,3µH
Optional Semper
(secure) Flash
Optional F-RAM
MPSSE
Channel B
3.3V
5V
P00.7
DP/DM
ADBUS2
ACBUS4
ADBUS1
DAP1
P21.7