Infineon AN84858, Быстрый старт

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Application Note 5 of 45 001-84858 Rev. *N
2021-03-23
PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
2 HSSP Firmware Architecture
HSSP for the target device is implemented in multiple layers using modular C code. These layers are as follows:
1.
SWD Protocol Physical layer
2.
SWD Protocol Packet layer
3.
HSSP Programming Steps layer
See Figure 1 for the flow of control among these layers.
Note: See the A_Hssp_Programmer project, which uses PSoC 5LP as the external host programmer,
attached with this application note for the implementation of this firmware.
Figure 1 HSSP Firmware Architecture
The HSSP Programming Steps layer uses the “Fetching Programming Data” interface to extract the
programming data from the source of the data (for example, the hex file data provided by any communication
interface
— I
2
C, SPI, UART, or USB or host flash — as Figure 1 shows. In addition, the “HSSP P rogramming Step ”
layer uses the HSSP Timeout Parameters interface to configure timeouts in its programming APIs.
Host Programmer
SWDIO
SWDCK
XRES
(1)
Target PSoC 4
device
RegisterDefines.h,
SWD_PhysicalLayer.h,
SWD_PhysicalLayer.c
SWD Protocol Physical Layer
SWD_PacketLayer.h,
SwdPacketLayer.c
SWD_UpperPacketLayer.h,
Swd_UpperPacketLayer.c
SWD Protocol Packet Layer
Timeout.h,
Timeout.c
HSSP Timeout
Parameters
ProgrammingSteps.h,
ProgrammingSteps.c
HSSP Programming Steps
DataFetch.h,
DataFetch.c
Fetching Programming
Data
HexImage.h,
HexImage.c
Programming
Data
main.c
Main application code
Device Acquire
Verify Silicon ID
Erase all Flash
Checksum Privileged Calculation
Program Flash
Exit HSSP Programming mode
Verify Flash
Program Protection Settings
Verify Protection Settings
Verify Checksum
HSSP Implementation Flow
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
(1)
For power cycle mode programming, device power rails need to be
toggled instead of the reset (XRES) pin