Infineon Technologies TC1784, Руководство пользователя

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TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-38 V1.1, 2011-05
Buses, V1.9
SBCU_
ECON SBCU Error Control
Capture Register 020
H
U, SV SV 3 Page 4-41
SBCU_
EADD SBCU Error Address
Capture Register 024
H
U, SV SV 3 Page 4-43
SBCU_
EDAT SBCU Error Data
Capture Register 028
H
U, SV SV 3 Page 4-44
– Reserved 02C
H
BE BE - -
SBCU_
DBCNTL SBCU Debug Control
Register 030
H
U, SV SV 1 Page 4-45
SBCU_
DBGRNT SBCU Debug Grant
Mask Register 034
H
U, SV SV 1 Page 4-48
SBCU_
DBADR1 SBCU Debug Address
Register 1 038
H
U, SV SV 1 Page 4-49
SBCU_
DBADR2 SBCU Debug Address
Register 2 03C
H
U, SV SV 1 Page 4-50
SBCU_
DBBOS SBCU Debug Bus
Operation Signals
Register 040
H
U, SV SV 1 Page 4-50
SBCU_
DBGNTT SBCU Debug Trapped
Master Register 044
H
U, SV BE 1 Page 4-52
SBCU_
DBADRT SBCU Debug Trapped
Address Register 048
H
U, SV BE 1 Page 4-54
SBCU_
DBBOST SBCU Debug Trapped
Bus Operation Signals
Register 04C
H
U, SV BE 1 Page 4-54
SBCU_
DBDAT SBCU Debug Data
Status Register 050
H
U, SV BE 1 Page 4-57
– Reserved 054
H
-
0F8
H
BE BE - -
SBCU_
SRC SBCU Service Request
Control Register 0FC
H
U, SV SV 3 Page 4-58
1) The absolute register address is calculated as follows:
Module Base Address ( Table 4-12 ) + Offset Address (shown in this column)
Table 4-13 Registers Overview - SBCU Control Registers
Short
Name Description Offset
Addr.
1)
Access Mode Reset
Class
Description
See
Read Write