TC1784
Analog to Digital Converter (ADC)
User´s Manual
23-94
V1.1, 2011-05
ADC, V1.3
23.2.15.4 Result FIFO Buffer
If a result register is not used as direct target for a conversion result, it can be
concatenated with other result registers of the same ADC kernel to form a result FIFO
buffer (first-in-first-out buffer mechanism). This allows to store measurement results and
to read them out later with a “relaxed” CPU access timing. It is possible to set up more
than one FIFO buffer structure with the available result registers.
A FIFO structure can be built by at least two “neighbor” result registers with the indices
x and z = x+1, where result register z represents the input and result register x
represents the output of the FIFO buffer. The conversion result has to be delivered by
the converter stage to the FIFO input, whereas the buffered data has to be read out from
the FIFO output.
The FIFO buffer function can be enabled by setting bit FEN in registers
.
In the example shown in
, the result registers have been configured to form
two FIFO buffers with two buffer stages (result registers 0/1 and 6/7, respectively), one
FIFO buffer with three buffer stages (result registers 2/3/4), whereas result register 5 is
used as “normal” result register without additional FIFO buffer functionality.
Figure 23-19 Result FIFO Buffers
If more than two result neighbor registers are concatenated to a FIFO buffer (from result
register z to result register x, with z > x), the one with the highest index (z) is always the
input and the one with the lowest index (x) is always the output. All intermediate result
registers y (x < y < z) are used as intermediate FIFO stages without data input or data
output functionality.
ADC_result_FIFO
result register 7
CPU read out
result register 6
result register 5
result register 4
result register 3
result register 2
result register 1
result register 0
CPU read out
CPU read out
CPU read out
conversion results
CH3
AD conversion
stage
conversion results
all other channels
(e.g. for scan)
conversion results
CH8
conversion results
CH2, 7, 10
Содержание TC1784
Страница 1: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Страница 3: ...User s Manual V1 1 2011 05 Microcontrollers TC1784 32 Bit Single Chip Microcontroller ...
Страница 950: ...TC1784 Direct Memory Access Controller DMA User s Manual 11 132 V1 1 2011 05 DMA V3 03 ...
Страница 1949: ...TC1784 General Purpose Timer Array GPTA v5 User s Manual 21 297 V1 1 2011 05 GPTA v5 V1 14 ...
Страница 2350: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG Doc_Number ...