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QUICK ST
AR
T GUIDE
EPC90132
EP
C –
PO
W
ER C
ON
VER
SION T
ECH
NOL
OG
Y L
EA
DER |
EPC
202
1 |
| 1
2
Figure 14: Dead-time and Bypass schematic
GND
GND
V CC
GND
V CC
GND
0.1 μF, 25 V
C610
V CC
V CC
GND
GND
GND
0.1 μF, 25 V
C612
V CC
0.1 μF, 25 V
C614
Qlow
Qup
10 k
R602
47 pF, 50 V
C602
GND
GND
10 k
R601
47 pF, 50 V
C601
GND
GND
In1
In2
100 pF, 50 V
C620
40 V 30 mA
D620
SDM03U40
120 Ω 1%
R620
GND
10 k
R604
GND
10 k
R603
GND
0.1 μF, 25 V
C611
Deadtime Lower
Deadtime Upper
Signal Polarity and Input Buffers
Bypass Mode Select
Polarity 0=Non-invert, 1= Invert
Polarity 0=Non-invert, 1= Invert
PolQup
PolQlow
DTQlow
Dual/Single PWM, Buck, and Boost Mode Selector
JP630
50 mil +Handle Blue
Dual Single
Buck Single Signal
Boost Single Signal
V CC
V CC
V CC
F ull By pass
No By pass
DT By pass
In1
In2
InBufQup
InBufQlow
100 pF, 50 V
C625
40 V 30 mA
D625
SDM03U40
120 Ω 1%
R625
GND
Default = 10 ns
Default = 10 ns
DTQup
74LV C1G99G
Reconfig Logic
Reconfig Logic
Reconfig Logic
G ND
4
2
3
7
V C C
8
5
1
6
U610
GND
GND
74LV C1G99G
Reconfig Logic
G ND
4
2
3
7
VCC
8
5
1
6
U611
Dual
In1
In1
In2
1
2
3
5
4
6
J630
Con3x2.05M
10 k
R605
GND
GND
V CC
74LVC1G99G
G ND
4
2
3
7
V C C
8
5
1
6
U612
GND
V C C
G ND
U615
Bilateral Analog Switch
GND
0.1μF , 25 V
C615
V CC
GND
V CC
In1
V CC
V CC
V CC
1
2
3
5
4
6
J640
Con3x2.05M
GND
VCC
VCC
VCC
VCC
74LVC1G99G
G ND
4
2
3
7
VCC
8
5
1
6
U614
GND
GND
10 k
R621
GND
SW byp
SW byp
10 k
R641
GND
V C C
G ND
U616
Bilateral Analog Switch
GND
0.1μF , 25 V
C616
V CC
GND
V CC
In2
SW byp
10 k
R643
GND
UseDT
GND
10 k
R626
GND
UseDT
SW byp
SW byp
UseDT
Output Buffers and Signal Select
PolQlow
PolQup
Dual
JP640
50mil +Handle Red