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WAFER-ULT3/ULT4 3.5" SBC
Page 76
All
D
EFAULT
Enable all cores in the processor package.
1
Enable one core in the processor package.
Hyper-threading [Enabled]
Use the
Hyper-threading
BIOS option to enable or disable the Intel Hyper-Threading
Technology.
Disabled
Disables the Intel Hyper-Threading Technology.
Enabled D
EFAULT
Enables the Intel Hyper-Threading Technology.
Intel
®
SpeedStep™ [Enabled]
Use the
Intel
®
SpeedStep™
option to enable or disable the Intel
®
SpeedStep
Technology.
Disabled
Disables the Intel
®
SpeedStep Technology.
Enabled
D
EFAULT
Enables the Intel
®
SpeedStep Technology.
C State [Disabled]
Use the
C State
option to enable or disable CPU C state.
Disabled D
EFAULT
Disables CPU C state.
Enabled
Enables CPU C state.
Содержание WAFER-ULT4
Страница 14: ......
Страница 15: ...WAFER ULT3 ULT4 3 5 SBC Page 1 Chapter 1 1 Introduction...
Страница 19: ...WAFER ULT3 ULT4 3 5 SBC Page 5 Figure 1 3 Connectors Solder Side...
Страница 25: ...WAFER ULT3 ULT4 3 5 SBC Page 11 Chapter 2 2 Packing List...
Страница 29: ...WAFER ULT3 ULT4 3 5 SBC Page 15 Chapter 3 3 Connectors...
Страница 60: ...WAFER ULT3 ULT4 3 5 SBC Page 46 Chapter 4 4 Installation...
Страница 84: ...WAFER ULT3 ULT4 3 5 SBC Page 70 Chapter 5 5 BIOS...
Страница 119: ...WAFER ULT3 ULT4 3 5 SBC Page 105 Appendix A A Regulatory Compliance...
Страница 121: ...WAFER ULT3 ULT4 3 5 SBC Page 107 Appendix B B BIOS Options...
Страница 124: ...WAFER ULT3 ULT4 3 5 SBC Page 110 Appendix C C Terminology...
Страница 128: ...WAFER ULT3 ULT4 3 5 SBC Page 114 Appendix D D Digital I O Interface...
Страница 131: ...WAFER ULT3 ULT4 3 5 SBC Page 117 Appendix E E Watchdog Timer...
Страница 134: ...WAFER ULT3 ULT4 3 5 SBC Page 120 Appendix F F Hazardous Materials Disclosure...