IEI Technology ROCKY-4786EVG, Руководство пользователя

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IEI
®
Technology, Corp .
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PCI power management registers by MCH
MAC Specific
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Optimized transmit and receive queues
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IEEE 802.3x-compliant flow-control support with software-controllable
thresholds
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Caches up to 64 packet descriptors in a single burst
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Programmable host memory receive buffers (256 B to 16 KB) and
cache line size (16 B to 256 B)
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Wide, optimized internal data path architecture
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40 KB configurable Transmit and Receive FIFO buffers
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Descriptor ring management hardware for transmit and receive
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Optimized descriptor fetching and writeback mechanisms
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Mechanism available for reducing interrupts generated by transmit
and receive operations
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Support for transmission and reception of packets up to 16 KB
PHY Specific
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Integrated for 10/100/1000 Mb/s full- and half-duplex operation
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IEEE 802.3ab Auto-Negotiation and PHY compliance and
compatibility
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State-of-the-art DSP architecture implements digital adaptive
equalization, echo and crosstalk cancellation
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PHY cable correction and diagnostics
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Automatic detection of cable lengths and MDI vs. MDI-X cable at all
speeds
Host Off-Loading
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Transmit and receive IP, TCP, and UDP checksum off-loading
capabilities
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Transmit TCP segmentation and advanced packed filtering
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IEEE 802.1Q VLAN tag insertion and stripping and packet filtering for
up to 4096 VLAN tags
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Jumbo frame support up to 16 KB
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Intelligent Interrupt generation (multiple packets per interrupt)
Manageability
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On-chip SMBus 2.0 port
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ASF 1.0 and 2.0
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Compliance with PCI Power Management v1.1/ACPI v2.0