IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

Страница: 58 / 58

58 ©2018 Integrated Device Technology, Inc. August 30, 2018
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit
www.idt.com/go/glossary . Integrated Device Technology, Inc.. All rights reserved.
Tech Support
www.IDT.com/go/support
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
VersaClock
®
6E Family Register Descriptions and Programming Guide
Revision History
Table 116. Power Up VDD check
VersaClock 6E products verify that all VDDs have ramped up before starting the configuration of circuits with settings from OTP. Because
of this feature, any VDD sequence can be used. For every output there is 1 bit to tell the chip to skip the verification of that output's VDD.
This bit can be used when the output is not used and the VDD will not be connected. It is still recommended to connect the VDD, but no
longer mandatory to allow the chip to start.
Register Bits Default Value Name Function
0x20 D7 0 bypass_sync1
“bypass_sync1” = 0: Include VDDO1 in VDD verification.
“bypass_sync1” = 1: Skip VDDO1 verification.
0x30 D7 0 bypass_sync2
“bypass_sync2” = 0: Include VDDO2 in VDD verification.
“bypass_sync2” = 1: Skip VDDO2 verification.
0x40 D7 0 bypass_sync3
“bypass_sync3” = 0: Include VDDO3 in VDD verification.
“bypass_sync3” = 1: Skip VDDO3 verification.
0x50 D7 0 bypass_sync4
“bypass_sync4” = 0: Include VDDO4 in VDD verification.
“bypass_sync4” = 1: Skip VDDO4 verification.
Revision Date Description of Change
August 30, 2018
▪
Removed references for 5P49V60.
▪
Added value for Cz in PLL Loop Filter Settings section.
November 6, 2017
Initial release.