IDT VersaClock 6E Series, Руководство по описанию регистров и программированию

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35 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Output Divider Fractional and Spread Settings ( Table 59 through Table 94 )
ODx_offset is the actual spread spectrum offset subtracted from the Fractional portion of the FODx divider N. It is the fractional portion of
the FODx divider. 30 bits spread over 4 registers. MSB is a sign bit. Set to 1 for negative numbers.
ODx_period bits are used to tune the spread rate from 30KHz to 63KHz according to the output frequency (period = Fout/Fss/2).13 bits
spread on 2 registers.
ODx_step is the Modulation step size; it sets the time rate of change or time slope of the output clock frequency. 24 bits spread on 3
registers.
If ODx_ssce = 0, contents of ODx_period and ODx_step are don't care only the ODx_offset are taken into account.
If ODx_ssce =1, means the spread is enabled for center spread offset. (See example of spread calculation “ Example of FOD calculation
for SSCE = 1 ”)
Table 57. RAM5 – 0x5D: Output Divider 4 Integer Part
Bits Default Value Name Function
D7 0
OD4_intdiv[11:4] Output divider 4 integer part has 12 bit spread over 2 registers x5D and x5E.
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Table 58. RAM5 – 0x5E: Output Divider 4 Integer Part
Bits Default Value Name Function
D7 0
OD4_intdiv[3:0] Output divider 4 integer part has 12 bit spread over 2 registers X5D and x5E.
D6 0
D5 0
D4 0
D3 0 unused bits Unused Factory reserved bit.
D2 0 unused bits Unused Factory reserved bit.
D1 0 unused bits Unused Factory reserved bit.
D0 0 unused bits Unused Factory reserved bit.