201
Tsi578 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
9. JTAG
Interface
This chapter describes the main features of the JTAG interface. It includes the following information:
•
•
“JTAG Device Identification Number” on page 202
•
“JTAG Register Access Details” on page 202
9.1
Overview
The JTAG interface in Tsi578 is fully compliant with IEEE 1149.6 B
oundary Scan Testing of Advanced
Digital Networks
as well as IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
standards. There are five standard pins associated with the interface (TMS, TCK, TDI, TDO and
TRST_b) which allow full control of the internal TAP (Test Access Port) controller.
The JTAG Interface has the following features:
•
Contains a 5-pin Test Access Port (TAP) controller, with support for the following registers:
— Instruction register (IR)
— Boundary scan register
— Bypass register
— Device ID register
— User test data register (DR)
•
IDT-specific pin (BCE) which allows full 1149.6 compliant boundary-scan tests. This pin should
be held high on the board.
•
Supports debug access of Tsi578’s configuration registers
•
Supports the following instruction opcodes:
— Sample/Preload
— Extest
— EXTEST_PULSE
(1149.6)
— EXTEST_TRAIN
(1149.6)
— Bypass
— Hi-Z
— IDCODE
— Clamp
— User data select
Содержание Tsi578
Страница 1: ...IDT Tsi578 Serial RapidIO Switch User Manual June 6 2016 Titl ...
Страница 20: ...About this Document 20 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...
Страница 102: ...4 Internal Switching Fabric Packet Queuing 102 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...
Страница 228: ...11 Signals Pinlist and Ballmap 228 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...
Страница 504: ...B Clocking P_CLK Programming 504 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...
Страница 526: ...Index 526 Tsi578 User Manual June 6 2016 Integrated Device Technology www idt com ...