2. Configurable Options > Switches
22
Tsi382 (BGA) Evaluation Board User Manual
60E2010_MA001_03
Integrated Device Technology
www.idt.com
Switch S4 controls the external clock PLL.
Switch S5 controls the PCIe clock multiplexer and the on-board PCIe reference clock PLL.
Switch S6 configures Tsi382’s power-up options.
Table 9: S4 Settings
Switch
Number
Description
Default
State
On/Off Setting
1
PLL Reset
ON
ON = PLL in reset. PLL clock outputs are low.
OFF = PLL is active and clock outputs are enabled.
2
XTAL select
OFF
ON = Clock source for PLL is reference clock from connector
J10
OFF = Clock source for PLL is a 25-MHz oscillator.
3
PLL select
OFF
ON = PLL is bypassed.
OFF = PLL is enabled. External clock source is multiplied as
per S3 setting
4
No function
-
-
Table 10: S5 Settings
Switch
Number
Description
Default
State
On/Off Setting
1
No Function
-
-
2
PCIe
on-board
PLL enable
ON
ON = On-board PCIe reference clock PLL is disabled.
OFF = On-board PCIe reference clock PLL is enabled.
3
PCIe clock
multiplexer
enable
OFF
ON = On-board PCIe clock multiplexer is disabled.
OFF = On-board PCIe clock multiplexer is enabled.
4
PCIe clock
source select
OFF
ON = On-board PCIe reference clock is used.
OFF = System PCIe reference clock is used.
Table 11: S6 Settings
Switch
Number
Description
Default
State
On/Off Setting
1
No function
-
-
2
Internal
arbiter option
ON
ON = Internal arbiter is enabled
OFF = Internal arbiter is disabled
