IDT EB8T5A Eval Board, Руководство пользователя

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Notes
EB8T5A Eval Board Manual 2 - 1 July 23, 2009
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Chapter 2
Installation of the EB8T5A
Eval Board
EB8T5A Installation
This chapter discusses the steps required to configure and install the EB8T5A evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB8T5A board is shipped with all jumpers and switches configured to their default settings. In most
cases, the board does not require further modification or setup.
Hardware Description
The PES8T5 is an 8-lane, 5-port PCI Express® switch. It is a peripheral chip that performs PCI Express
based switching with a feature set optimized for high performance applications such as servers and
storage. It provides fan-out and switching functions between a PCI Express upstream port and 4 down-
stream ports or peer-to-peer switching between downstream ports.
The EB8T5A has four PCI Express downstream ports, accessible through four x4 open-ended connec-
tors.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express
x4 slot.
– PCI Express Endpoint Cards capable of training x1 link.
Host System
The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x4 configuration through a PCI Express x4 slot is required to take full
advantage of the PES8T5’s capabilities.
Reference Clocks
The PES8T5A requires a differential reference clock. The EB8T5A derives this clock from a common
source which is user-selectable. The common source can be either the host system’s reference clock or the
onboard clock generator. Selection is made by resistor switch described in Table 2.1.
Clock Configuration Switch - S3[3]
S3[3] Clock Source
ON Onboard Reference Clock – Use onboard clock generator
OFF Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection