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3. RapidIO Lanes > Port and Lane Initialization Sequence

CPS-1848 User Manual

76

June 2, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

7. The link-level flow control mode (transmitter or receiver controlled) is negotiated as part of the exchange of status control

symbols. The CPS-1848 always attempts to use transmitter-controlled flow control, and reverts to receiver-controlled flow
control if the link partner does not support the transmitter method.
— To disable the use of transmitter-controlled flow control on a port, set the

Port {0..17} Operations

.TX_FLOW_CTL_DIS bit.

— The flow control mode that is currently selected is indicated in

Port {0..17} Status and Control Register

8. Once at least seven consecutive status control symbols have been received, and at least 15 have been transmitted, the port

asserts the PORT_OK bit and clears the PORT_UNINIT bit in the

Port {0..17} Error and Status CSR

. Thereafter, the port can

exchange packets and detect/report transmission errors.

The above sequence reliably initializes single or multi-lane links as long as at least one of the redundant lanes in each direction
is working. However, consistent with the RapidIO Specification (Rev. 2.1), the initialization sequence for 4x ports was not
designed to operate correctly when connected to multiple, separate 1x ports on the redundant lanes. This type of configuration
is not supported.

3.4.1

Signal Quality Optimization

The default values for the signal quality settings are sufficient for channels that are compliant with the RapidIO specification’s
short- and medium-reach channel definitions (50 cm with up to two connectors). However, the default signal quality settings
may need to change for long channels and/or high lane speeds.

The CPS-1848 supports two methods for optimizing the signal quality of a lane (see

• Transmit emphasis
• Receiver Decision Feedback Equalization (DFE)

Transmit emphasis changes the characteristics of the transmit signal based on the bit that was previously transmitted, and the
bit that will be transmitted after the current bit. Receiver DFE changes the received signal to reduce electrical effects created
by previously received bits.

Figure 13: Optimizing Lane Signal Quality

Clear error conditions on the link, which may have occurred during link initialization.

Transmitter Pre- and

Post- Emphasis

Settings

Receiver DFE Tap

Adjustments

Tx Link Partner

Rx Link Partner

IDLE2 Comands for Pre- and

Post-Emphasis Adjustment

IDLE2 Command Acknowledgements

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Содержание CPS-1848

Страница 1: ...CPS 1848 User Manual Central Packet Switch Formal Status June 2 2014 Titl...

Страница 2: ...terized errata will be made available upon request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibili...

Страница 3: ...30 2 3 1 Packet Routing Overview 30 2 3 2 Unicast Programming Model 31 2 3 3 Multicast Programming Model 33 2 3 4 Programming Examples 34 2 4 Flow Control 38 2 4 1 Transmitter and Receiver Controlled...

Страница 4: ...Polynomials 84 3 6 2 User Defined Patterns 84 3 6 3 PRBS Pattern Generator 85 3 6 4 PRBS Pattern Checker and Log Revision C 85 4 Switch Fabric 87 4 1 Key Features 87 4 2 Switch Fabric Architecture 88...

Страница 5: ...ation 137 6 3 2 Physical Layer Events Notification 139 6 3 3 Lane Event Notification 146 6 3 4 I2C Event Notification 146 6 3 5 JTAG 1149 1 Event Notification Revision A B Only 147 6 3 6 Configuration...

Страница 6: ...d AC Extest Compliance 183 8 3 Test Instructions 184 8 4 Device ID Register 184 8 5 Initialization and Reset 185 8 6 Configuration Register Access Revision A B 185 8 6 1 Configuration Register Access...

Страница 7: ...0 5 1 Port Maintenance Block Header Register 229 10 5 2 Port Link Timeout Control CSR 230 10 5 3 Port General Control CSR 230 10 5 4 Port 0 17 S RIO Extended Features Base Addresses 231 10 5 5 Port 0...

Страница 8: ...rt 0 17 Implementation Specific Error Report Enable Register 291 10 10 10 Broadcast Port Error Report Enable Register 294 10 10 11 Broadcast Port Implementation Specific Error Report Enable Register 2...

Страница 9: ...17 Trace 2 Mask 4 Register 325 10 13 32 Port 0 17 Trace 3 Value 0 Register 326 10 13 33 Port 0 17 Trace 3 Value 1 Register 326 10 13 34 Port 0 17 Trace 3 Value 2 Register 327 10 13 35 Port 0 17 Trace...

Страница 10: ...obal Device Configuration Registers 351 10 14 1 Device Control 1 Register 351 10 14 2 Configuration Block Error Report Register 353 10 14 3 Aux Port Error Report Enable Register 354 10 14 4 RapidIO Do...

Страница 11: ...eceived Packets Dropped Counter Register 393 10 16 25 Port 0 17 VC0 Transmitted Packets Dropped Counter Register 394 10 16 26 Port 0 17 VC0 TTL Packets Dropped Counter Register 395 10 16 27 Port 0 17...

Страница 12: ...ne Control Register 434 10 20 13 Broadcast Lane PRBS Generator Seed Register 438 10 20 14 Broadcast Lane Error Detect Register 439 10 20 15 Broadcast Lane Error Rate Enable Register 440 10 20 16 Broad...

Страница 13: ...Physical Layer Error Management Programming Model Flow Chart 109 Figure 21 Implementation Specific Physical Layer Error Management Programming Model Flow Chart 110 Figure 22 Lane Error Management Prog...

Страница 14: ...with 7 bit Slave Address ADS is 0 181 Figure 41 Read Protocol with 7 bit Slave Address ADS is 0 182 Figure 42 JTAG Write Access Timing Diagram 186 Figure 43 JTAG Read Access Timing Diagram 186 Figure...

Страница 15: ...Routing Packets Correctly 65 Table 18 Packet Counters and Configuration Issues Switch Cannot Transmit Packets 66 Table 19 Configuration and Status Values to Check Switch Cannot Transmit Packets 67 Ta...

Страница 16: ...otification Control 140 Table 54 Port Write Programming Model Registers and Fields 148 Table 55 Standard Type 1 Port Write Format 149 Table 56 IDT Type 2 Port Write Format 151 Table 57 Error Log Event...

Страница 17: ...ription of the CPS 1848 s registers References provides a list of specifications referred to in this manual Additional Resources In addition to this user manual which explains the functionality of the...

Страница 18: ...nformation in Table 35 Table 44 Table 52 and Table 60 to align with the Logical Transport Layer Control Capture CSR Updated the first three bullets in Error Log Event Notification Programming Model to...

Страница 19: ...d other minor improvements throughout the document February 7 2013 Formal Manual Updated Maintenance Packet Routing Updated the caution in Generating a Reset Request Added a caution to Hot Extraction...

Страница 20: ...he 20 31 fields to reserved in Lane 0 47 DFE 1 Register and Broadcast Lane DFE 1 Register Changed the definition of the 19 21 and 25 26 fields in the following registers to reserved Lane 0 47 Error Re...

Страница 21: ...G Clock Constraints Updated step 7 in I2C EEPROM Format Updated Received Retry Count Trigger Congestion Isolation Updated Link Initialization and Register Initialization Updated Port Reconfiguration O...

Страница 22: ...ed references to SerDes TX to RX Loopback Mode and Port Level Loopback features and their respective register functionality SERDES_LPBK and PORT_LEVEL_LPBK_SWITCH_SIDE_EN fields Completed other minor...

Страница 23: ...ation RapidIO switching supports standard RapidIO routing functionality including unicast and up to 40 multicast groups The CPS 1848 exceeds the RapidIO Specification Rev 2 1 to support broadcast rout...

Страница 24: ...ticast masks with broadcast capability Global route and per port local route modes Supervision Fault Management Congestion Management Compliant with RapidIO Specification Rev 2 1 Part 8 Error Manageme...

Страница 25: ...h fabric support a separate routing path for maintenance packets which provides register access from any RapidIO port In addition the I2C Interface and the JTAG 1149 1 Interface also support access to...

Страница 26: ...formance to power ratio allows unprecedented compute density to enable 3G and 4G systems Switched architecture allows highly scalable system for micro and macro BTS implementations Carrier grade 6 25...

Страница 27: ...vice system memory reads and writes Figure 4 Military Open VPX System Application 1 4 3 Video and Imaging Application Benefits 40 multicast masks per port provides strong support for broadcasting or m...

Страница 28: ...t Control Symbols Port Reconfiguration Operations Reset Control Symbol Processing Hot Extraction Insertion Packet Trace and Filtering Packet Generation and Capture Packet Transfer Validation and Debug...

Страница 29: ...er and transmitter controlled flow control S RIO based reset support Packet retransmission management Link maintenance and software assisted error recovery Packet transmission cancellation Link error...

Страница 30: ...implementation specific registers for both the routing tables and for multicast In addition debug features such as packet trace and filtering augment the normal packet routing The following sections d...

Страница 31: ...tries Configuration destID Select CSR specifies the destID whose routing is affected by writes to the Standard Route Table Entry Configuration Port Select CSR The Standard Route Table Entry Configurat...

Страница 32: ...is allows packets with the same destID to be routed differently depending on which port they are received This can be used to partition the switch or to create virtual networks The Route Port Select R...

Страница 33: ...ved the maintenance request The source ID of the request packet becomes the destID of the response packet and the destID of the request packet becomes the sourceID of the response packet For Revision...

Страница 34: ...3 3 3 Broadcast Routing The RapidIO Specification Rev 2 1 requires that multicast packets are not replicated to the port that they are received on This allows one multicast mask to be shared among man...

Страница 35: ...5 Route destID 0x7A00 0x7AFF to the default port Standard Route Table Entries Configuration destID Select CSR 0x70 0x00007A00 Standard Route Table Entry Configuration Port Select CSR 0x74 0x000000DE D...

Страница 36: ...Route destID 0x43xx to port 5 for all ports Broadcast Domain Route Table Register 0 255 0xE0050C 0x00000005 Route destID 0x5500 to 0x55FF according to the Device Routing Table for all ports Broadcast...

Страница 37: ...t CSR 0x80 0x00200040 0x00200A10 0x00200B10 0x00200C10 Associate DestID 0x03 with Multicast Mask 0x20 on all ports except port 11 The association is performed in two steps 1 Associate all ports with t...

Страница 38: ...del Transmitter and receiver controlled flow control decide which packets to send based on a packet s priority The CPS 1848 supports the four standard RapidIO priorities numbered 0 to 3 where 3 is the...

Страница 39: ...itialization or reset see Table 6 The watermark values in the Port 0 17 Watermarks Register should be set based on the buffer size of the link partner and the required traffic characteristics for pack...

Страница 40: ...The packet is not acknowledged 4 Tracking of outstanding Link Request Input Status error recovery control symbols is reset Lane 0 47 Control Register LANE_DIS Lane disable enable Port reset see PORT_S...

Страница 41: ...ding packets to the reset port some packets may exist in the final buffer after the reset It is also possible for maintenance responses to be sent after the reset because maintenance requests with a h...

Страница 42: ...and the CLR bit in this register should be set to 1 This will cause all outstanding unacknowledged packets to be dropped Alternatively the procedure for hot insertion can reset the link partner and d...

Страница 43: ...Prevent acceptance of new packets from the HS LP 4 Reset and or extract the HS LP 5 Confirm the reset extraction by reception of an extraction event as described below 6 Prepare the port for the inser...

Страница 44: ...N_PORT_FAIL_ENC_EN and DROP_PKT_EN are set see Event Isolation Port 0 17 Operations Register F40004 0x100 Y 0x10000000 PORT_INT_EN or 0x08000000 PORT_PW_EN Ensure at least one of PORT_INT_EN or PORT_P...

Страница 45: ...17 Control 1 CSR 0x15C 0x20 Y 0xXXXXXXXF Ensure PORT_LOCKOUT STOP_ON_PORT_FAIL_ENC_EN and DROP_PKT_EN are set Note Responses may be in flight to from the HS LP at this point Device Control 1 Register...

Страница 46: ...port as described in Packet Routing This should stop requests from being issued to the HS LP Port 0 17 Control 1 CSR 0x15C 0x20 Y 0xXXXXXXXF Ensure PORT_LOCKOUT STOP_ON_PORT_FAIL_ENC_EN and DROP_PKT_...

Страница 47: ...threshold to detect an OUTPUT_FAIL condition Port 0 17 Error and Status CSR if one or more errors occur Lane 0 47 Error Rate Enable Register 0xFF8010 0x100 lane_num 0x00000003 Enable error reporting...

Страница 48: ...d synchronizing ackIDs depends on whether the HS LP or another node in the system is the Recovery Controller and the specific link configuration Common scenarios involving the CPS 1848 are described i...

Страница 49: ...he port Port 0 17 Control 1 CSR 0x15C 0x20 port_num Value is port specific Ensure PORT_LOCKOUT STOP_ON_PORT_FAIL_ENC_EN and DROP_ENABLE are cleared 3 Reset the HS LP and CPS 1848 port Y simultaneously...

Страница 50: ...s not a CPS 1848 Remote the register address and value written are implementation specific 2 Disable and clear error conditions that prevent transmission of link requests by the HS LP Local Port 0 17...

Страница 51: ...known clear ackIDs If the CPS 1848 Remote port is not known skip step 6 and proceed to step 7 Port 0 17 Local ackID CSR 0x000148 0x20 Y CPS 1848 Remote 0x80000000 Clear ackIDs on the CPS 1848 Remote p...

Страница 52: ...r HS LP Local inbound ackID while retaining existing outstanding outbound ackID Port 0 17 Local ackID CSR 0x00148 0x20 Y CPS 1848 Remote 0x81000000 Clear outstanding outbound ackID on CPS 1848 Remote...

Страница 53: ...for packet forwarding Each S RIO port provides a set of four uniquely configurable 160 bit comparison values that can selectively be applied using a bit mask to the first 160 bits of each packet that...

Страница 54: ...res Each S RIO port supports a trace port functionality The user can define which output port is enabled for the Trace function For a specific device all packets that match the Trace criteria from all...

Страница 55: ...ets that do not match the trace criteria With this configuration packets received by a port that are to be routed to the trace port as defined by that port s route table will be dropped by the device...

Страница 56: ...hat are generated as a result of trace matches Trace match based port writes are enabled via TRACE_PW_EN in the Port 0 17 Operations Register Standard port write packet generation is not affected by t...

Страница 57: ...son value at that port Each S RIO port can enable disable packet trace and packet filtering simultaneously for each unique comparison value If both packet filtering and packet trace are enabled and a...

Страница 58: ...t where the response packet is captured in the Final Buffer The response packet can then be read out There are two scenarios for the use of PGC mode The first sends a packet directly to the link partn...

Страница 59: ...cket generation and capture to operate PORT_OK status can be achieved by connecting to a link partner or by connecting the port s TX lanes to its RX lanes Table 13 PGC Mode Example Connectivity Test S...

Страница 60: ...ata of maintenance packet at priority 0 0x100134 0x08000100 Bytes 4 7 of Maintenance Read 0x100130 0x00005001 Clear SOP for remaining data writes 0x100134 0x00001DFE Bytes 8 11 of Maintenance Read 0x1...

Страница 61: ...0x00006004 Enable read access to final buffer priority 1 queue 0x100144 Read 0x0000XXXX Bytes 8 11 of Maintenance Read Response where XXXX is the most significant 2 bytes of the link partners Device I...

Страница 62: ...ters NACK d packets are not counted as received or dropped Port 0 17 VC0 Retry Symbols Transmitted Counter Register Increments when a retry CS is sent No relation to other counters retried packets are...

Страница 63: ...Counter Register is not 0 on the port that should be receiving packets and this counter is 0 on the port that should be transmitting the packets this indicates a routing configuration issue Port 0 17...

Страница 64: ...s CSR PORT_OK If this bit is set to 0 the link is not connected to the link partner For more information see the Debugging IDT S RIO Gen2 Switches Using RapidFET JTAG PORT_ERR If this bit is set to 1...

Страница 65: ...ty enabled and which packets will be dropped check the FILTER_x_EN bits in the Port 0 17 Operations Register If the registers in Table 17 are set correctly then each route must be verified individuall...

Страница 66: ...ry The link partner is configured to accept packets but is congested Debug the link partner s ability to accept packets Port 0 17 VC0 Transmitted Packets Dropped Counter Register This counter indicate...

Страница 67: ...h output port has detected an error and error recovery is not complete Packets will not be transmitted until OUTPUT_ERR_STOP has been cleared Check that the Port Link Timeout Control CSR has been init...

Страница 68: ...ance If you are unable to resolve issues in your system using the information in this document please contact IDT RapidIO support As part of the request please submit the following register values for...

Страница 69: ...Lane to Port Mapping Lane and Port Speeds Lane PLL and Port Power Down Port and Lane Initialization Sequence Loopback Capabilities Bit Error Rate Testing Figure 12 shows a block diagram of an S RIO La...

Страница 70: ...ee the CPS 1848 Datasheet Software can also control the device s port width settings and lane to port mapping using the Quadrant Configuration Register Table 20 shows the supported mapping of lanes to...

Страница 71: ...13 17 Unused 01 1 2x 1 4 5 1 2x 13 6 7 5 4x 5 20 23 9 4x 9 36 39 17 Unused 10 1 2x 1 4 5 1 2x 13 6 7 5 4x 5 20 23 9 2x 9 36 37 9 2x 17 38 39 11 1 2x 1 4 5 1 1x 13 6 1 1x 17 7 5 4x 5 20 23 9 4x 9 36 3...

Страница 72: ...0 determines the CPS 1848 s quadrant configurations Software can also control the quadrant configurations based on the value of QUADx_CFG in the Quadrant Configuration Register The least significant...

Страница 73: ...oth ports and requires a per port reset of both ports The register accesses listed in Table 22 are required to reconfigure the lane speeds of the ports Each SerDes has a single PLL The PLL can be conf...

Страница 74: ...47 Control Register 0xXXXXX0A Set TX_RATE and RX_RATE fields to 0b01 Set LANE_DIS field to 0 0xFF8300 Lane 0 47 Control Register 0xXXXXX0A Set TX_RATE and RX_RATE fields to 0b01 Set LANE_DIS field to...

Страница 75: ...fy board layouts the CPS 1848 can automatically detect and correct when the positive and negative traces of a differential pair for a lane are inverted Lane inversion status for each lane is located i...

Страница 76: ...tion is working However consistent with the RapidIO Specification Rev 2 1 the initialization sequence for 4x ports was not designed to operate correctly when connected to multiple separate 1x ports on...

Страница 77: ...to configured reset and preset tap values The reset and preset values for each of the two pre emphasis taps are configured through writes to the Lane 0 47 Status 2 CSR The output waveform has three pa...

Страница 78: ...d the step size of the previous bits to the last bit increases The following graph shows the change in the step size as the register DAC value is increased The dB value is calculated as 20log previous...

Страница 79: ...AP value is increased the step size from the initial bit amplitude to the subsequent bit amplitude increases The following graph shows the change in the step size The dB value is calculated as 20log s...

Страница 80: ...register accesses The programming model for software control of the receiver DFE taps makes use of a paired select control bit and a tap value field for each tap The following are the pairs of select...

Страница 81: ...he above steps are completed for a port the Port 0 17 Error Rate CSR ERR_RATE_CNTR field can be read to determine the number of errors seen since the counter was last cleared to 0 The above algorithm...

Страница 82: ...ack points that can be used for test and fault isolation purposes These loopback points are displayed in Figure 14 and are discussed in the following sections Figure 14 Loopback Locations Port Block L...

Страница 83: ...0 and 11 can only operate in 4x mode 10 bit loopback is not functional on those ports 3 5 1 2 8 bit Loopback Mode 8 bit loopback mode is controlled on individual lanes through the LPBK_8BIT_EN bit of...

Страница 84: ...ial see CCITT O 1S1 ITU T O 150 section 5 6 SONET 2 x31 x28 1 For additional definition of the polynomial see ITU T O 150 section 5 8 and XAUI IEEE Std 802 3 2008 3 x10 x7 1 For additional definition...

Страница 85: ...PS 1848 can check user defined patterns in 10 bit mode only see Lane 0 47 Control Register PRBS_UNIDIR_BERT_MODE_EN Table 25 Programming Model for CPS 1848 Data Generation Link Partner Checking Step O...

Страница 86: ...Set Lane 0 47 Control Register PRBS_TRAIN to 0 Errors are not reported when in training mode 8 Read Lane 0 47 PRBS Error Counter Register Check for errors other than from configuration while running a...

Страница 87: ...latency for more information see Performance Each port can buffer up to 12 packets from the link partner and up to 34 packets to be sent to the link partner Non blocking across all ports and all prior...

Страница 88: ...for Revision C a hop count equal to 0 are handled as a separate flow by the Switch Fabric There is a separate path between each Input Buffer and the centralized Maintenance Transactions handling bloc...

Страница 89: ..._EN field Packets accepted by the Input Buffer are managed using Virtual Output Queues VoQs There is a set of VoQs for maintenance packets with a hop count of 0 and one set of VoQs for each Crosspoint...

Страница 90: ...sent to has an entry added to it for that packet When a packet that is being multicast is selected for transfer the other VoQs are checked to see if that packet is the first packet in the VoQ If it is...

Страница 91: ...evel Block Transfers from the Input Buffer to the Maintenance function are performed on a strict priority basis If the priority of the maintenance packets is the same among the Input Buffers a round r...

Страница 92: ...eters 1 Register BUF_ALLOC field as displayed in Table 26 The CPS 1848 supports an additional option for Final Buffer allocation If BUF_ALLOC in the Switch Parameters 1 Register is 0 then FB_ALLOC in...

Страница 93: ...hroughput does not include control symbols retried packets or other non packet data transmitted received on a link K and R characters 5 1 2 Latency Latency is the amount of time between when a packet...

Страница 94: ...e first bit if the destination has no available buffers These factors should be considered when creating a system timing budget see Table 30 5 2 Performance Monitoring The main purpose of the performa...

Страница 95: ...rds on each port The calculations of the packet rate packet size and utilization are completed externally 5 2 2 Congestion Detection Congestion in the S RIO ports can be detected by monitoring the cou...

Страница 96: ...ver a few parameters that require adjustments for specific usage case as listed below Input Buffer Crosspoint Buffer and Final Buffer Allocation Buffer Allocation Size Switching Arbitration mode Store...

Страница 97: ...d and is given priority over all other flows in the queue of the same SRIO priority 5 3 1 2 2 Output Scheduler The output scheduler uses a proportional fairness algorithm to select from multiple cross...

Страница 98: ...d flow control is the default mode for each port In this mode the transmitter sends packets only when the link partner has indicated that it has available input buffer space to receive them Buffer wat...

Страница 99: ...e latency numbers under no congestion with default arbitration and watermark settings The numbers are based on the same ingress and egress port widths and baud rates The minimum latency is the minimum...

Страница 100: ...nto a packet to maintain the baud rate of the port The appearance of a bubble indicates that the egress port is under utilized In a typical application an S RIO packet stream consists of an Start of P...

Страница 101: ...ingress port and egress port will always maintain line rates This means there will be no retry of packets at the ingress and no bubble occurring in the egress packet streams This is true for any payl...

Страница 102: ...ports When any of the egress ports has a line rate lower than the ingress port s bandwidth retries occur at the ingress port In this situation the egress port maintains its line rate For example when...

Страница 103: ...rwarding delay minus the minimum forwarding delay through the switch Table 33 4x 2x 1x Multicast Event Control Symbol Latency Numbers Ingress and Egress Port Width Ingress and Egress Baud Rate Gbaud R...

Страница 104: ...function interrupts port writes none should be triggered when an event is detected 3 Isolation automatic reactions to events How can the CPS 1848 prevent the event from impacting the remainder of the...

Страница 105: ...e IDT Port Write PGC Interrupt Standard Port Write Filter Event Detected JTAG Event Detected JTAG Event Enables Lane Event Detected Lane Event Enables I2C Event Detected I2C Event Enables Physical Eve...

Страница 106: ...rd Port Write Filter Event Detected Config Event Detected Config Event Enables Lane Event Detected Lane Event Enables I2C Event Detected I2C Event Enables Physical Event Detected Physical Event Enable...

Страница 107: ...andard and IDT port writes see Port Write Formats Programming Model and Generation For more information about the Error Log functionality see Error Log Event Notification Programming Model A detected...

Страница 108: ...and are indicated in the Logical Transport Layer Error Detect CSR Information about the packet that contained the detected error is latched in the Logical Transport Layer deviceID Capture CSR Logical...

Страница 109: ...r log depending on the configuration of the registers displayed in Figure 20 Figure 20 Standard Physical Layer Error Management Programming Model Flow Chart Port writes and interrupts are disabled by...

Страница 110: ...Register because these occur at a rate consistent with the bit error rate of the lanes associated with each port and therefore are part of the normal operation of the system PORT_n_ERR_RPT_EN IMP_SPEC...

Страница 111: ...ed by default for individual Lane events Individual lane errors should not be enabled in the Lane 0 47 Error Report Enable Register because these occur at a rate consistent with the bit error rate of...

Страница 112: ...ptured in the error log depending on the configuration of the registers displayed in Figure 23 Figure 23 I2C Error Management Programming Model Flow Chart AUX_PORT_ERR_CAPT_EN 0x020000 AUX_PORT_ERR_RP...

Страница 113: ...wing types of events Logical and Transport Layer Events Physical Layer Events Lane Events I2C Events JTAG Events Revision A B Only Configuration Block Events Trace and Filter Events Packet Generation...

Страница 114: ...Logical Transport Layer Address Capture Register Standard no address Information is captured in the Logical Transport Layer deviceID Capture CSR and Logical Transport Layer Control Capture CSR No inf...

Страница 115: ...have any information captured The values in the Information Captured column are described in Table 36 Maintenance read received with data Always Detected Logical Transport Layer Error Enable CSR IMP_S...

Страница 116: ...ontains the least significant 4 bytes of the destriped 8 bytes of data Register The written register data that caused the event is captured This information is in the following registers Port 0 17 Att...

Страница 117: ...cket with bad CRC Always Detected Port 0 17 Error Rate Enable CSR PKT_CRC_ERR_EN 1 Packet Port 0 17 Error Detect CSR PKT_CRC_ERR Received a packet that exceeds 276 bytes Always Detected Port 0 17 Erro...

Страница 118: ...te Enable CSR IMP_SPEC_ERR_EN 1 and Port 0 17 Implementation Specific Error Rate Enable Register CRC_EVENT_EN 1 No Info Port 0 17 Implementation Specific Error Detect Register CRC_EVENT and Port 0 17...

Страница 119: ...Packet Port 0 17 Implementation Specific Error Detect Register RTE_ISSUE Received a packet that references a disabled port and is dropped Port 0 17 Control 1 CSR PORT_DIS 1 Port 0 17 Error Rate Enable...

Страница 120: ...RETRY_EN 1 Control Symbol Port 0 17 Implementation Specific Error Detect Register MANY_RETRY Discarded a received non maintenance packet Note The packet is not accepted by the receiver but the transmi...

Страница 121: ...EN 1 and Port 0 17 Implementation Specific Error Rate Enable Register RETRY_EN 1 Control Symbol Port 0 17 Implementation Specific Error Detect Register RETRY Received a retry control symbol with unexp...

Страница 122: ...0 17 Implementation Specific Error Detect Register UNEXP_EOP Port 0 17 Error Detect CSR PRTCL_ERR Received stomp outside of a packet Always Detected Port 0 17 Error Rate Enable CSR IMP_SPEC_ERR_EN 1 a...

Страница 123: ...Detect Register IDLE_IN_PKT Loss of alignment Always Detected Port 0 17 Error Rate Enable CSR IMP_SPEC_ERR_EN 1 and Port 0 17 Implementation Specific Error Rate Enable Register LOA_EN 1 No Info Port 0...

Страница 124: ...ied Detection Enable Any register settings required to enable detection of the event Always Detected means that there are no controls to disable detection of the event Information Capture Enable The r...

Страница 125: ...e 0 47 Data Capture 0 Register 30 Remote receiver trained state Table 39 Lane Event Enable and Information Capture Summary Event Detection Enable Information Capture Enable Information Captured Lane i...

Страница 126: ...etection Enable Information Capture Enable Information Captured I2C checksum error I2C Master Control Register CHKSUM_DIS 0 Aux Port Error Capture Enable Register I2C_CHKSUM_ERR_E N Aux Port Error Det...

Страница 127: ...ssociated with this event This event is called PGC_CMPL 6 2 9 Error Log Events All events can be reported to the Error Log The Error Log functionality is summarized in Figure 25 Note The Error Report...

Страница 128: ...detected then the bit in the Error Log Match Status Register associated with that Error Log Match Register 0 7 is set Setting bits in the Error Log Match Status Register does not constitute an event...

Страница 129: ...12 0x4C Lane 13 0x4D Lane 14 0x4E Lane 15 0x4F Lane 16 0x50 Lane 17 0x51 Lane 18 0x52 Lane 19 0x53 Lane 20 0x54 Lane 21 0x55 Lane 22 0x56 Lane 23 0x57 Lane 24 0x58 Lane 25 0x59 Lane 26 0x5A Lane 27 0x...

Страница 130: ...ne 45 0x6D Lane 46 0x6E Lane 47 0x6F Port 0 0x2A Port 1 0x29 Port 2 0x34 Port 3 0x33 Port 4 0x32 Port 5 0x31 Port 6 0x3C Port 7 0x3B Port 8 0x3A Port 9 0x39 Port 10 0x3D Port 11 0x3E Port 12 0x1C Port...

Страница 131: ...ransport Event Encoding Table 44 defines the Error Codes to be captured in the Error Log associated with the Logical Layer Transport Errors defined in the RapidIO Specification Rev 2 1 Part 8 6 2 9 3...

Страница 132: ...control symbol with unexpected ackID 0x87 UNEXP_ACKID UNEXP_ACKID Acknowledgement control symbol with unexpected ackID 0x88 UNEXP_ACKID RETRY_ACKID Control symbol not acknowledged 0x8A CS_NOT_ACC N A...

Страница 133: ..._SPEC UNEXP_EOP Port initialization TX acquired 0x85 IMP_SPEC PORT_INIT Discarded a received non maintenance packet 0x86 IMP_SPEC RX_DROP Received an accepted control symbol with unexpected ackID 0x87...

Страница 134: ...al error state and is dropped 0xA3 IMP_SPEC RTE_ISSUE Packet was dropped due to TTL event 0xA4 IMP_SPEC TTL_EVENT Received a packet with a CRC error with CRC error suppression enabled 0xA6 IMP_SPEC CR...

Страница 135: ...f I2 C error reporting is enabled each error can be sent to the Error Log when detected Table 47 Error Log Lane Level Encoding Error Error Code Corresponding Detect Bit in Lane 0 47 Error Detect Regis...

Страница 136: ...ng The Trace Filter and PGC mode events have their own special encoding that is not associated with any other status bits These events are listed in the following table Table 49 JTAG Errors and Codes...

Страница 137: ...the link should be considered inoperable due to the error rate Both link degraded and link failed thresholds create RapidIO standard events that can result in port writes being sent and or interrupt...

Страница 138: ...Control 1 Register LT_INIT_EN 1 Logical Transport Layer Error Report Enable Register UNSUP_TRAN_EN 1 Maintenance read size invalid Logical Transport Layer Error Report Enable Register IMP_SPEC_ERR_EN...

Страница 139: ...formation on how the Error Log can assert interrupts and send IDT port writes see Error Log Event Notification Programming Model Maintenance transaction field error Logical Transport Layer Error Repor...

Страница 140: ...N 1 and Port 0 17 Operations Register PORT_PW_EN 1 Port 0 17 Error Report Enable Register PKT_ILL_ACKID_EN 1 and Port 0 17 Operations Register PORT_INT_EN 1 Port 0 17 Error Report Enable Register PKT_...

Страница 141: ...INT_EN 1 Port 0 17 Error Report Enable Register LINK_TIMEOUT_EN 1 and Port 0 17 Operations Register PORT_LOG_EN 1 Received a packet when an error rate threshold event has occurred and drop packet mode...

Страница 142: ...N 1 and Port 0 17 Operations Register PORT_PW_EN 1 Port 0 17 Implementation Specific Error Report Enable Register UNEXP_ACKID_EN 1 and Port 0 17 Operations Register PORT_INT_EN 1 Port 0 17 Implementat...

Страница 143: ...ister TX_DROP_EN 1 and Port 0 17 Operations Register PORT_PW_EN 1 Port 0 17 Implementation Specific Error Report Enable Register TX_DROP_EN 1 and Port 0 17 Operations Register PORT_INT_EN 1 Port 0 17...

Страница 144: ...Report Enable Register RETRY_EN 1 and Port 0 17 Operations Register PORT_PW_EN 1 Port 0 17 Implementation Specific Error Report Enable Register RETRY_EN 1 and Port 0 17 Operations Register PORT_INT_EN...

Страница 145: ...r UNEXP_STOMP_EN 1 and Port 0 17 Operations Register PORT_PW_EN 1 Port 0 17 Implementation Specific Error Report Enable Register UNEXP_STOMP_EN 1 and Port 0 17 Operations Register PORT_INT_EN 1 Port 0...

Страница 146: ...nt To enable interrupt notification for any I2C event the I2C Master Control Register I2C_INT_EN bit must be set Once this bit is set I2 C events that are enabled as described in I2C Events will cause...

Страница 147: ...vents that are enabled as described in Configuration Block Events will cause a port write to be sent To enable interrupt notification for any configuration event the Configuration Block Error Report R...

Страница 148: ...s must be configured before port writes can be successfully received The type of port write format that has been received can be determined based on the length of the port write payload For endpoints...

Страница 149: ...ed simultaneously with a Configuration Block error then the LT error should be reported first The Error source column lists the potential sources of CPS 1848 errors All other columns represent the val...

Страница 150: ...the current value of the Port 0 17 Error Detect CSR from the port in which the error is detected Note that multiple port level errors can be indicated with the same port write if multiple bits are set...

Страница 151: ...el The encoding of fields in IDT port writes is discussed in Error Log Events The full maintenance packet generated are as displayed in Table 56 The fields in the in the IDT Port Write Payload are in...

Страница 152: ...to the upper 4 bits called the error group and the lower four bits called the error number The method of selection depends on the following pairs of fields in the Error Log Match Register 0 7 ERR_SOUR...

Страница 153: ...Control 2 Register 6 3 11 3 Error Management Stop The Error Manager will stop if a specific error is detected and the Error Log Match Register 0 7 STOP_EN bit is set The user can stop the Error Manage...

Страница 154: ...Error and Status CSR and or if the Error Rate Failed threshold has been met or exceeded in the Port 0 17 Error Rate Threshold CSR 0 1 The port discards packets that receive a Packet not accepted contr...

Страница 155: ...C retransmit limit When the CPS 1848 CRC retransmission limit is enabled packets transmitted that have exceeded the programmed CRC retransmission limit are discarded The port s Port 0 17 Error and Sta...

Страница 156: ...leared non maintenance packets routed to that port are dropped The port sets Port 0 17 Error and Status CSR OUTPUT_DROP and Port 0 17 Implementation Specific Error Detect Register TX_DROP bit The port...

Страница 157: ...atus and Control Register CLR_MANY_RETRY 6 4 3 TTL Event Isolation For users who are unable to make use of the CPS 1848 VoQ Fairness Starvation Avoidance function time to live functionality enables th...

Страница 158: ...nd Recovery After an event is detected and reported the software entity that receives the report must perform any reconfiguration of the system necessary to continue system operation The software enti...

Страница 159: ...highly unlikely transmission error Maintenance write received without data Logical Transport Layer Error Detect CSR IMP_SPEC_ERR 0 This error could indicate a hardware software failure in the originat...

Страница 160: ...licited acknowledgement control symbol Port 0 17 Error Detect CSR CS_ACK_ILL 0 May indicate loss of ackID synchronization See Loss of AckID Synchronization Link timeout Port 0 17 Error Detect CSR LINK...

Страница 161: ...the link partner has isolated itself The system should prevent non maintenance packets from being routed to this port and or configure an isolation function for this port 6 lack of resources should n...

Страница 162: ...acket to be transmitted Port 0 17 Implementation Specific Error Detect Register TX_DROP 0 then Port 0 17 Error Detect CSR IMP_SPEC_ERR 0 If packets are not expected to be sent to ports with the Port 0...

Страница 163: ...eceiver controlled flow control If retries should not be received see the Received Retry Count Trigger Congestion Isolation Received a retry control symbol with unexpected ackID Port 0 17 Implementati...

Страница 164: ...n error Port initialization TX required Port 0 17 Implementation Specific Error Detect Register PORT_INIT 0 then Port 0 17 Error Detect CSR IMP_SPEC_ERR 0 Indicates the link completed reinitialization...

Страница 165: ...e CMD field in the register Support is provided for the following CMD field values 0b011 Reset device 0b100 Input status 6 5 2 1 2 Port 0 17 Link Maintenance Request CSR Reset Command Field When a wri...

Страница 166: ...kets that have been previously transmitted without the device having received an acknowledgement are retransmitted using ackIDs that start from the value written into this register 6 5 2 1 8 Outstandi...

Страница 167: ...event Loss of descrambler sync Lane 0 47 Error Detect Register DESCRAM_SYNC 0 Transmission error Hardware error recovery is invoked only if the link and port have been initialized as indicated by Por...

Страница 168: ...d not sent four bytes for a write or requested more than four bytes for a read transaction Table 64 JTAG Event Clearing and Handling Revision A B Only Event Clearing The Event Event Handling Discussio...

Страница 169: ...Register Port 0 17 Trace Match Counter Value 2 Register and or Port 0 17 Trace Match Counter Value 3 Register counters for the port where the trace match occurred Filter match occurred Clear the Port...

Страница 170: ...r specification 7 2 Master Slave Configuration The CPS 1848 provides an external signal MM_N to configure the device in Master mode or Slave mode out of reset When this signal is tied to GND it config...

Страница 171: ...le Whether or not a checksum comparison is performed to validate the download is also programmable These configuration sequence options are established by writes to the I2C Master Control Register and...

Страница 172: ...d IDT recommends a subsequent port re initialization or reset for more information see Port Reconfiguration Operations Table 67 EEPROM Register Address Map EEPROM Address Byte Level Addresses Bits EEP...

Страница 173: ...ect CRC The following algorithm will generate the CRC 16 expected at the end of the EEPROM unsigned short icrc16 unsigned char data int numBytes unsigned short remainder 0 unsigned char crc 16 unsigne...

Страница 174: ...inder 0 memset crc 0 sizeof crc for b 0 b numBytes b byte data b bit_Pos_Mask 0x80 for bit_Pos 0 bit_Pos 8 bit_Pos carry crc 15 if bit_Pos_Mask byte serial_data 1 else serial_data 0 for i 15 i 0 i if...

Страница 175: ...mat Example Table 68 Register Map Example Register Value Comment 0x00015C 0x00600000 Block 1 0xE00000 0x01 Block 2 0xE00004 0x02 0xE00008 0x03 0xE0000C 0x04 0xE00010 0x05 0xE00014 0x06 0xE00018 0x07 0...

Страница 176: ...ally through an interrupt or port write For information on enabling interrupt and port write notification see I2C Event Notification 0x000C 0x08 Start of Block 2 Register count 9 0x000D 0x38 Address 0...

Страница 177: ...Slave mode on the I2 C bus supports the following cases 1 Master device to CPS 1848 a Master device addresses the CPS 1848 as a slave b Master device master transmitter sends data to the CPS 1848 sla...

Страница 178: ...anual 178 June 2 2014 Formal Status This document is confidential and is subject to an NDA Integrated Device Technology Figure 27 Bit Transfer on the I2 C Bus Figure 28 START and STOP Signaling Figure...

Страница 179: ...aster Addressing a Slave with a 7 bit Address Transfer Direction is Not Changed Figure 32 Master Reads a Slave Immediately After the First Byte Figure 33 Combined Format Figure 34 Master Addresses a S...

Страница 180: ...ins A slave address should also be used that is unique to each device on the bus IDT also recommends to avoid using reserved addresses as specified in the I2C Specification such as CBUS addresses Prov...

Страница 181: ...A P STOP Input Data 31 24 Input Data 23 16 Input Data 15 8 Input Data 7 0 A ACK 73 82 92 55 64 A 1 ACK R W R 1 W 0 Device Address 9 8 1 1 1 1 0 S A Sr repeated START DATA A ACK A ACK DATA DATA A ACK...

Страница 182: ...Slave Address ADS is 0 46 55 64 73 83 Memory Address 23 18 Memory Address 17 10 Memory Address 9 2 27 36 18 SLAVE ADDR A 0 ACK R W 0 S START 9 R 1 W 0 Device Address 6 0 DATA A ACK A ACK DATA DATA A A...

Страница 183: ...Test Instructions Device ID Register Initialization and Reset Configuration Register Access Revision A B Configuration Register Access Revision C JTAG Clock Constraints Boundary Scan 8 1 Overview The...

Страница 184: ...parity bit in the 8th bit As per the IEEE 1149 1 Specification the first 7 bits of the Vendor ID will be the first 7 bits of the EIA JEP106 code discarding the parity bit Thus the JTAG IDCODE read fro...

Страница 185: ...the use of the Configuration Register Access opcode writes and reads to any register are possible The same JTAG instruction is used for both writes and reads of the Configuration Register space Bit ze...

Страница 186: ...ode for this report is defined in JTAG Error Encoding Revision A B Only 8 6 2 Configuration Register Access Reads When bit 0 of the data stream is 1 data shifted out is read from the address specified...

Страница 187: ...able 74 If this minimum delay requirement is violated and command B is applied too soon after command A command A may not have enough time to finish when its status is shifted out In this case the REA...

Страница 188: ...machine that is implemented in the CPS 1848 s TAP Controller Each inter state arc is annotated with the TMS input value needed to traverse that arc The CPS 1848 JTAG register access mechanism allows o...

Страница 189: ...command A The orange line shows the sequence of states needed to apply command B The red line shows the inter command delay that must be applied after Command A before command B can be started Table 7...

Страница 190: ...nal command a NOP command can be shifted in while the Read status and data are shifted out Figure 46 JTAG Register Access Read Timing Diagram Update DR Run Test Idle Exit1 DR Select DR Capture DR Shif...

Страница 191: ...acing must be 40 ns see Figure 47 Figure 47 JTAG Clock Constraints 8 9 Boundary Scan JTAG instructions are provided to make all the device inputs observable and all the outputs controllable All extern...

Страница 192: ...configuration pins For more information about power up reset electrical requirements see the CPS 1848 Datasheet 9 1 2 Resets after Power Up There are four methods to reset the CPS 1848 1 Driving the R...

Страница 193: ...amic configuration RapidIO Assembly Identification CAR Override RapidIO Assembly Information CAR Override Port 0 17 Control 1 CSR ENUM_B and PORT_LOCKOUT bit fields if necessary If PORT_LOCKOUT is set...

Страница 194: ...ister 4 Configuration no ordering is required for the following steps a Program the route table as described in Programming Examples b Revision A B only Change Port 0 17 Lane Synchronization Register...

Страница 195: ...ard register that defines the response timeout for the physical level protocol such as receipt of a link response control symbol after sending a link request In the CPS 1848 this standard register is...

Страница 196: ...ntrol CSR If the system does not use request packets that require responses during normal operation the TTL function does not need to be enabled For example systems that make exclusive use of NWRITE S...

Страница 197: ...ction Registers Implementation Specific Error Logging Registers Special Error Registers PLL Registers Lane Control Registers Error Management Broadcast Registers 10 1 Overview The CPS 1848 register fi...

Страница 198: ...8 backward compatible with previous IDT 1 3 compliant switch devices IDT specific functions and associated registers are similarly backward compatible where possible 10 1 4 Register Type Field Definit...

Страница 199: ...ters with Software Assisted Error Recovery 0x000100 Port Maintenance Block Header Register PORT_MAINT_BLK_HEAD 0x000120 Port Link Timeout Control CSR PORT_LINK_TO_CTL_CSR 0x00013C Port General Control...

Страница 200: ...al Transport Layer deviceID Capture CSR LT_DEVICEID_CAPT_CSR 0x00101C Logical Transport Layer Control Capture CSR LT_CTL_CAPT_CSR 0x001028 Port Write Target deviceID CSR PW_TARGET_DEVICEID_CSR 0x00102...

Страница 201: ..._0_CSR 0x002014 Lane 0 47 Status 1 CSR LANE_0_STATUS_1_CSR 0x002018 Lane 0 47 Status 2 CSR LANE_0_STATUS_2_CSR 0x00201C Lane 0 47 Status 3 CSR LANE_0_STATUS_3_CSR 0x002020 Lane 0 47 Status 4 CSR LANE_...

Страница 202: ...Register AUX_PORT_ERR_CAPT_EN 0x020004 Aux Port Error Detect Register AUX_PORT_ERR_DET 0x020008 Configuration Block Error Capture Enable Register CFG_ERR_CAPT_EN 0x020010 Configuration Block Error Det...

Страница 203: ..._RPT_EN 0x03FF10 Broadcast Lane Error Report Enable Register BCAST_LANE_ERR_RPT_EN Packet Generation and Capture Registers 0x100100 Port 0 17 Packet Generation and Capture Mode Configuration Register...

Страница 204: ...gister 0xE40010 Port 0 17 Trace 0 Value 4 Register 0xE40014 Port 0 17 Trace 0 Mask 0 Register PORT_0_TRACE_0_MASK_ 0 4 0xE40018 Port 0 17 Trace 0 Mask 1 Register 0xE4001C Port 0 17 Trace 0 Mask 2 Regi...

Страница 205: ...3 Mask 0 Register PORT_0_TRACE_3_MASK_ 0 4 0xE40090 Port 0 17 Trace 3 Mask 1 Register 0xE40094 Port 0 17 Trace 3 Mask 2 Register 0xE40098 Port 0 17 Trace 3 Mask 3 Register 0xE4009C Port 0 17 Trace 3...

Страница 206: ...Register 0xE4F030 Broadcast Trace 1 Value 2 Register 0xE4F034 Broadcast Trace 1 Value 3 Register 0xE4F038 Broadcast Trace 1 Value 4 Register 0xE4F03C Broadcast Trace 1 Mask 0 Register BCAST_TRACE_1_MA...

Страница 207: ...te Control Register PW_CTL 0xF2002C RapidIO Assembly Identification CAR Override ASSY_IDENT_CAR_OVRD 0xF20030 RapidIO Assembly Information CAR Override ASSY_INF_CAR_OVRD 0xF20040 Device Soft Reset Reg...

Страница 208: ...7 Trace Match Counter Value 3 Register PORT_0_TRACE_CNTR_3 0xF40030 Port 0 17 Filter Match Counter Value 0 Register PORT_0_FILTER_CNTR_0 0xF40034 Port 0 17 Filter Match Counter Value 1 Register PORT_0...

Страница 209: ...Address 0xF40900 Port 9 Starting Address 0xF40A00 Port 10 Starting Address 0xF40B00 Port 11 Starting Address 0xF40C00 Port 12 Starting Address 0xF40D00 Port 13 Starting Address 0xF40E00 Port 14 Starti...

Страница 210: ...0xFF0040 PLL 4 Starting Address 0xFF0050 PLL 5 Starting Address 0xFF0060 PLL 6 Starting Address 0xFF0070 PLL 7 Starting Address 0xFF0080 PLL 8 Starting Address 0xFF0090 PLL 9 Starting Address 0xFF00A...

Страница 211: ..._SEED 0xFFFF0C Broadcast Lane Error Detect Register BCAST_LANE_ERR_DET 0xFFFF10 Broadcast Lane Error Rate Enable Register BCAST_LANE_ERR_RATE_EN 0xFFFF14 Broadcast Lane Attributes Capture Register BCA...

Страница 212: ...ters communicate a device s capabilities 10 3 1 Device Identity CAR Register Name DEV_IDENT_CAR Reset Value 0x0374_0038 Register Offset 0x000000 Bits 0 1 2 3 4 5 6 7 00 07 DEVICE 08 15 DEVICE 16 23 VE...

Страница 213: ...s 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 MAJOR_REV MINOR_REV 16 23 Reserved 24 31 Reserved JTAG_REV Bits Name Description Type Reset Value 0 7 Reserved Reserved RO 0 8 10 MAJOR_REV Device Major Revision...

Страница 214: ...assembly supplier For more information see RapidIO Assembly Identification CAR Override FR 0 16 31 VENDOR Assembly Vendor Identifier This field identifies the manufacturing vendor of the assembly con...

Страница 215: ...ption Type Reset Value 0 BRIDGE The device can bridge between S RIO and another non S RIO interface 0 Not supported 1 Supported FR 0 1 MEM The device does not have physically addressable local address...

Страница 216: ...CRC error 0 Not supported 1 Supported Note This is defined in RapidIO Specification Rev 1 3 but is not specified in the RapidIO Specification Rev 2 1 FR 1 26 CRF Critical Request Flow support 0 Not s...

Страница 217: ...gister Offset 0x000014 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 TOTAL 24 31 PORT Bits Name Description Type Reset Value 0 15 Reserved Reserved RR 0 16 23 TOTAL The total number of S RI...

Страница 218: ...5 Reserved Reserved RR 0 16 NREAD Device can source a read operation 0 Not supported FR 0 17 NWRITE Device can source a write operation 0 Not supported FR 0 18 SWRITE Device supports a streaming write...

Страница 219: ...atomic clear operation 0 Not supported FR 0 28 Reserved Reserved RR 0 29 PW Device can source a port write operation 1 Supported FR 1 30 31 Reserved Reserved RR 0 Register Name SWITCH_MCAST_SUP_CAR R...

Страница 220: ...9 Switch Route Table Entries Table Limit CAR Register Name SWITCH_RTE_TBL_LIM_CAR Reset Value 0x0000_00FF Register Offset 0x000034 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 MAX_DESTID 2...

Страница 221: ...ssociation support 0 Not supported FR 0 1 PER_PORT Per Ingress port association support 0 Not supported FR 0 2 15 MAX_DESTID The maximum number of destIDs that can be associated with a multicast mask...

Страница 222: ...Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 HOST_BASE_DEVICEID 24 31 HOST_BASE_DEVICEID Bits Name Description Type Reset Value 0 15 Reserved Reserved RO 0 16 31 HOST_BASE_DEV ICEID Base...

Страница 223: ...3 4 5 6 7 00 07 EXTD_EN Reserved 08 15 Reserved 16 23 DESTID_MSB 24 31 DESTID_LSB Bits Name Description Type Reset Value 0 EXTD_EN Extended Configuration Enable 0 Disable 1 Enable RW 0 1 15 Reserved R...

Страница 224: ...et Value 0 7 PORT_3 This is the output port that all messages intended for DESTID_LSB 3 are sent RW 0 8 15 PORT_2 This is the output port that all messages intended for DESTID_LSB 2 are sent RW 0 16 2...

Страница 225: ...4 5 Standard Route Table Entry Default Port CSR Register Name RTE_DEFAULT_PORT_CSR Reset Value 0x0000_0000 Register Offset 0x000078 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24...

Страница 226: ...ription Type Reset Value 0 15 MCAST_MASK Defines the multicast mask to be modified queried as determined by the MASK_CMD RW 0 16 23 EGRESS_PORT Defines the port number that is modified queried by the...

Страница 227: ...er Name MCAST_ASSOC_SEL_CSR Reset Value 0x0000_0000 Register Offset 0x000084 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID_LSB 16 23 MASK 24 31 MASK Bits Name Description Type Reset Value 0 7 DES...

Страница 228: ...15 Reserved 16 23 Reserved 24 31 TYPE CMD Reserved STATUS Bits Name Description Type Reset Value 0 23 Reserved Reserved RO 0 24 TYPE 0 Small transport association 1 Large transport association RW 0 25...

Страница 229: ...ssisted Error Recovery which contains status information and control values for various physical layer functions of the RapidIO processing element These registers are defined in this section 10 5 1 Po...

Страница 230: ...ding link response 10 5 3 Port General Control CSR Register Name PORT_LINK_TO_CTL_CSR Reset Value 0xFFFF_FF00 Register Offset 0x000120 Bits 0 1 2 3 4 5 6 7 00 07 TIMEOUT 08 15 TIMEOUT 16 23 TIMEOUT 24...

Страница 231: ...ment is confidential and is subject to an NDA Integrated Device Technology 10 5 4 Port 0 17 S RIO Extended Features Base Addresses Port Address 0 0x000140 1 0x000160 2 0x000180 3 0x0001A0 4 0x0001C0 5...

Страница 232: ...t Register Name PORT_ 0 17 _LINK_MAINT_REQ_CSR Reset Value 0x0000_0000 Register Offset 0x000140 0x20 port_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved CMD Bits...

Страница 233: ...STATUS LINK_STATUS Bits Name Description Type Reset Value 0 VALID If the previous Link Request causes a Link Response then this bit indicates that the Link Response has been received and the status fi...

Страница 234: ...ts This bit should be written only when trying to recover a failed link This bit will return 0 when read WO 0 1 Reserved Reserved RO 0 2 7 INBOUND Input port next expected ackID Note Bit 2 is availabl...

Страница 235: ...T Bits Name Description Type Reset Value 0 IDLE2 Indicates whether the port supports IDLE2 sequence for throughput rates of less than 6 25 Gbaud 0 Not supported 1 Supported RO 1 1 IDLE2_EN Controls wh...

Страница 236: ...ived RO 0 13 OUTPUT_RETRY_ STOP 1 Output Retry Port is stopped The output port received a Packet Retry control symbol and is in the output retry stopped state RO 0 14 OUTPUT_ERR 1 Output Error was enc...

Страница 237: ...6 For example Too many response timeouts occur 16 A link response is received with an invalid ackID Part 6 also requires that this bit be reset when it is read However this functionality creates an i...

Страница 238: ...L _ENC_EN DROP_PKT _EN PORT_LOC KOUT PORT_TYP E Bits Name Description Type Reset Value 0 1 PWIDTH Indicates the port width modes supported by the port 0b00 No support for 2x or 4x 0b01 No support for...

Страница 239: ...ey are unable to receive transmit any packets or control symbols Note When PORT_DIS is 1 ackID values are cleared to zero For more information see Port 0 17 Local ackID CSR RW 0 9 OUTPUT_PORT_E N Outp...

Страница 240: ...xx_xx1x Suppress CRF 0 priority 1 re transmission 0bxxxx_x1xx Suppress CRF 0 priority 2 re transmission 0bxxxx_1xxx Suppress CRF 0 priority 3 re transmission 0bxxx1_xxxx Suppress CRF 1 priority 0 re t...

Страница 241: ...led by the state of the OUTPUT_PORT_EN and INPUT_PORT_EN bits in this register When this bit is set 1 this port is stopped and is not enabled to issue or receive any packets the input port can still f...

Страница 242: ...ES_EN SCRAM_DI S Reserved Bits Name Description Type Reset Value 0 3 Reserved Reserved RO 0 4 AUTOBAUD 0 Automatic baud rate discovery is not supported FR 0 5 27 Reserved Reserved RO 0 28 INACT_LANES_...

Страница 243: ...t data characters are neither scrambled in the transmitter before transmission nor descrambled in the receiver upon reception The transmit scrambler remains enabled for the generation of pseudo random...

Страница 244: ...or a RapidIO processing element These registers are defined in this section 10 6 1 VC Register Block Header Register Register Name VC_REGISTER_BLK_HEAD Reset Value 0x1000_000A Register Offset 0x000600...

Страница 245: ...s for logical and physical layer error management for RapidIO devices These registers are defined in this section 10 7 1 Error Management Extensions Block Header Register Register Name ERR_MGT_EXTENSI...

Страница 246: ...ue 0x0000_00000 Register Offset 0x001008 Bits 0 1 2 3 4 5 6 7 00 07 Reserved ILL_TRAN Reserved 08 15 UNSOL_RE SP UNSUP_TR AN Reserved 16 23 Reserved 24 31 Reserved IMP_SPEC _ERR Bits Name Description...

Страница 247: ...ion of the cause Register Name LT_ERR_EN_CSR Reset Value 0x0000_00000 Register Offset 0x00100C Bits 0 1 2 3 4 5 6 7 00 07 Reserved ILL_TRAN_ EN Reserved 08 15 UNSOL_RE SP_EN UNSUP_TR AN_EN Reserved 16...

Страница 248: ...r Detect CSR and can be unlocked using same method Register Name LT_DEVICEID_CAPT_CSR Reset Value 0x0000_00000 Register Offset 0x001018 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID_LSB 16 23 SOU...

Страница 249: ...TTYPE 08 15 Reserved 16 23 Reserved 24 31 IMP_SPEC Bits Name Description Type Reset Value 0 3 FTYPE Format type associated with the error RW 0 4 7 TTYPE Transaction type associated with the error RW...

Страница 250: ...without a payload A response packet with an error status is generated 0b1 0b0001_0000 Maintenance Packet Received was Too Small or Too Large MTC_PKT_SIZE_ERR Triggered if the maintenance packet heade...

Страница 251: ...set Value 0x0000_00000 Register Offset 0x001028 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID 16 23 LARGE Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 DESTID_MSB Most signif...

Страница 252: ...o Live CSR Register Name PKT_TTL_CSR Reset Value 0x0000_00000 Register Offset 0x00102C Bits 0 1 2 3 4 5 6 7 00 07 TTL 08 15 TTL 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 1...

Страница 253: ...ntial and is subject to an NDA Integrated Device Technology 10 7 8 Port Error Management Register Base Addresses Port Address 0 0x001040 1 0x001080 2 0x0010C0 3 0x001100 4 0x001140 5 0x001180 6 0x0011...

Страница 254: ...IDLE1_ER R Reserved 24 31 Reserved LR_ACKID _ILL PRTCL_ER R Reserved DELIN_ER R CS_ACK_IL L LINK_TIME OUT Bits Name Description Type Reset Value 0 IMP_SPEC_ERR 1 Detected an IDT implementation specifi...

Страница 255: ...link response with an ackID that is not outstanding RW 0 27 PRTCL_ERR 1 Detected a protocol error RW 0 28 Reserved Reserved RO 0 29 DELIN_ERR 1 Detected a delineation error RW 0 30 CS_ACK_ILL 1 Detec...

Страница 256: ...ame Description Type Reset Value 0 IMP_SPEC_ERR_EN 1 Enable the capture and counting of the corresponding error in the Port 0 17 Error Detect CSR RW 0 1 8 Reserved Reserved RO 0 9 CS_CRC_ERR_EN 1 Enab...

Страница 257: ...1 Enable the capture and counting of the corresponding error in the Port 0 17 Error Detect CSR RW 0 28 Reserved Reserved RO 0 29 DELIN_ERR_EN 1 Enable the capture and counting of the corresponding err...

Страница 258: ...id 0b011 Long control symbol only error capture registers 0 and 1 are valid 0b100 Implementation specific data is logged 0b101 Reserved 0b110 Undefined S bit error 0b111 Reserved RW 0b000 3 7 ERR_TYPE...

Страница 259: ...must write the Port 0 17 Attributes Capture CSR to set the VALID bit after writing the packet control symbol information in the other capture registers For base address information see Port Error Man...

Страница 260: ..._1_CSR Reset Value 0x0000_00000 Register Offset 0x001050 0x40 port_num Bits 0 1 2 3 4 5 6 7 00 07 CAPT_1 08 15 CAPT_1 16 23 CAPT_1 24 31 CAPT_1 Bits Name Description Type Reset Value 0 31 CAPT_1 Bytes...

Страница 261: ...chnology 10 7 15 Port 0 17 Capture 3 CSR For base address information see Port Error Management Register Base Addresses Register Name PORT_ 0 17 _CAPT_3_CSR Reset Value 0x0000_00000 Register Offset 0x...

Страница 262: ...RR_RATE_BIAS The error rate bias value 0x00 Do not decrement the error rate counter 0x01 Decrement every 1 ms 34 0x02 Decrement every 10 ms 34 0x04 Decrement every 100 ms 34 0x08 Decrement every 1 s 3...

Страница 263: ...l can cause multiple physical layer events to be detected The leaky bucket counter is incremented by 1 for each erroneous control symbol and packet regardless of the number of physical layer events de...

Страница 264: ...00106C 0x40 port_num Bits 0 1 2 3 4 5 6 7 00 07 FAIL_THRESH 08 15 DEGR_THRESH 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 FAIL_THRESH The threshold trigger value for repor...

Страница 265: ...us information and control values for each physical lane supported by a RapidIO device These registers are defined in this section 10 8 1 Lane 0 47 Status Base Addresses Lane Address 0 0x002010 1 0x00...

Страница 266: ...nd is subject to an NDA Integrated Device Technology 27 0x002370 28 0x002390 29 0x0023B0 30 0x0023D0 31 0x0023F0 32 0x002410 33 0x002430 34 0x002450 35 0x002470 36 0x002490 37 0x0024B0 38 0x0024D0 39...

Страница 267: ...see Lane Status Registers Register Name LANE_STATUS_BLK_HEAD Reset Value 0x0000_0000D Register Offset 0x002000 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Descript...

Страница 268: ..._SYNC_ CHG RX_TRAIN ED_CHG Reserved STATUS_1 STATUS_CSR Bits Name Description Type Reset Value 0 7 PORT 0x00 Port 0 0x01 Port 1 0x11 Port 17 RO Undefined 8 11 LANE The number of the lane within the po...

Страница 269: ...s reset to 0 when the register is read 0 The state of lane_sync did not change since the bit was last read 1 The state of lane_sync changed since the bit was last read RR 0 26 RX_TRAINED_CHG Indicates...

Страница 270: ...reset 1 An IDLE2 sequence has been received at some time since the lane was last reset RO 0 1 CURRENT This field indicates whether the information in this register that is collected from the IDLE2 se...

Страница 271: ...dard support All others are reserved RO 0b000 8 11 LP_LANE Receiver lane number of the link partner port detected in IDLE2 these bits do not apply in IDLE1 0x0 Lane 0 0x1 Lane 1 0x2 Lane 2 0x3 Lane 3...

Страница 272: ...served NEG1_ON_PRE 08 15 NEG1_ON_ PRE Reserved POS1_ON_PRE 16 23 POS1_ON_ PRE Reserved NEG1_ON_RST 24 31 Reserved POS1_ON_RST Bits Name Description Type Reset Value 0 3 Reserved Reserved RO 0 4 8 NEG1...

Страница 273: ..._5_ EN GBAUD_6p 25_EN NEG1_CMD 16 23 NEG1_CM D POS1_CMD NEG1_TAP 24 31 NEG1_TAP POS1_TAP Bits Name Description Type Reset Value 0 UNUSED Reserved RW 1 1 Reserved Reserved RO 1 2 AMP_PROG_EN Local Tran...

Страница 274: ...0x1 Reset remote pre emphasis 0x2 Preset remote pre emphasis 0x3 Increment 1 tap 0x4 Decrement 1 tap 0x5 Increment 1 tap 0x6 Decrement 1 tap All others are reserved WO 0 17 20 POS1_CMD Local Pre empha...

Страница 275: ...OR_STATUS CC_MONIT OR_EN 16 23 CC_MONITOR_THRESH 24 31 CC_MONITOR_THRESH Bits Name Description Type Reset Value 0 UNUSED Reserved RW 1 1 13 Reserved Reserved RO 0 14 CC_MONITOR_ST ATUS 1 Clock Compen...

Страница 276: ...R 0b00000 Broadcast access to all Port Route Table 0b00001 Access is for Port 0 Route Table 0b00010 Access is for Port 1 Route Table 0b00011 Access is for Port 2 Route Table 0b00100 Access is for Port...

Страница 277: ...e received 0b00000 Broadcast access to all Port Route Table 0b00001 Access is for Port 0 Route Table 0b00010 Access is for Port 1 Route Table 0b00011 Access is for Port 2 Route Table 0b00100 Access is...

Страница 278: ...tial and is subject to an NDA Integrated Device Technology 10 9 3 Port n Watermarks Base Addresses Port Offset from Base 0 0x011000 1 0x011010 2 0x011020 3 0x011030 4 0x011040 5 0x011050 6 0x011060 7...

Страница 279: ...rt n Watermarks Base Addresses The broadcast version of this register is Broadcast Watermarks Register Register Name PORT_ 0 17 _WM Reset Value 0x0000_20C4 Register Offset 0x011000 0x10 port_num Bits...

Страница 280: ...0 Register Offset 0x01F000 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved PRIO_2 16 23 PRIO_2 PRIO_1 24 31 PRIO_1 PRIO_0 Bits Name Description Type Reset Value 0 13 Reserved Reserved RO 0 14 19 PR...

Страница 281: ...ster Name AUX_PORT_ERR_CAPT_EN Reset Value 0x0000_0000 Register Offset 0x020000 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved JTAG_ERR _EN I2C_CHKS UM_ERR_ EN UNEXP_...

Страница 282: ...not 32 bit aligned Note This bit is applicable to CPS 1848 Revision A B only RW 0 27 I2C_CHKSUM_ERR 0 No error 1 In Master mode at the end of a configuration image update the checksum value in the ima...

Страница 283: ...gth read or write transaction RW 0 Register Name CFG_ERR_CAPT_EN Reset Value 0x0000_0000 Register Offset 0x020008 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved BAD_M...

Страница 284: ...a valid port on the device The write will still occur and any other valid ports will be changed RW 0 28 BAD_RTE 0 No error 1 A route table or pointer table has been read and its value reference result...

Страница 285: ...e user has attempted to program the Domain Route Table with a multicast mask number or The Multicast Mask Port CSR was written to with an invalid mask or The Multicast Association Selection CSR was wr...

Страница 286: ...r The contents of this register are unlocked simultaneously with the values in the Logical Transport Layer Error Detect CSR Register Name IMPL_SPEC_LT_ADDR_CAPT Reset Value 0x0000_0000 Register Offset...

Страница 287: ...0x03100C Bits 0 1 2 3 4 5 6 7 00 07 Reserved ILL_TRAN_ EN Reserved 08 15 UNSOL_RE SP_EN UNSUP_TR AN_EN Reserved 16 23 Reserved 24 31 IMP_SPEC_ERR_EN Bits Name Description Type Reset Value 0 3 Reserved...

Страница 288: ...ential and is subject to an NDA Integrated Device Technology 10 10 7 Port 0 17 Error Report Enable Base Addresses Port Base Address 0 0x031044 1 0x031084 2 0x0310C4 3 0x031104 4 0x031144 5 0x031184 6...

Страница 289: ...C_E RR_EN UNEXP_AC KID_EN CS_NOT_A CC_EN PKT_ILL_A CKID_EN PKT_CRC_ ERR_EN PKT_ILL_SI ZE_EN Reserved 16 23 IDLE1_ER R_EN Reserved 24 31 Reserved LR_ACKID _ILL_EN PRTCL_ER R_EN Reserved DELIN_ER R_EN C...

Страница 290: ...ing of the corresponding error in the Port 0 17 Error Detect CSR RW 0 27 PRTCL_ERR_EN 1 Enable the reporting of the corresponding error in the Port 0 17 Error Detect CSR RW 0 28 Reserved Reserved RO 0...

Страница 291: ...INIT _EN PORT_WID TH_EN IDLE_IN_P KT_EN LOA_EN BAD_CTL_ EN REORDER _EN Bits Name Description Type Reset Value 0 ERR_RATE_EN 1 Enable reporting of the corresponding error in the Port 0 17 Implementatio...

Страница 292: ...EN 1 Enable reporting of the corresponding error in the Port 0 17 Implementation Specific Error Detect Register RW 1 19 RETRY_ACKID_EN 1 Enable reporting of the corresponding error in the Port 0 17 Im...

Страница 293: ...Implementation Specific Error Detect Register RW 1 29 LOA_EN 1 Enable reporting of the corresponding error in the Port 0 17 Implementation Specific Error Detect Register RW 1 30 BAD_CTL_EN 1 Enable re...

Страница 294: ...Name Description Type Reset Value 0 IMP_SPEC_ERR_ EN 1 Enable the reporting of errors to the corresponding bit in the Port 0 17 Error Detect CSR RW 0 1 8 Reserved Reserved RO 0 9 CS_CRC_ERR_EN 1 Enab...

Страница 295: ...ERR_EN 1 Enable the reporting of errors to the corresponding bit in the Port 0 17 Error Detect CSR RW 0 28 Reserved Reserved RO 0 29 DELIN_ERR_EN 1 Enable the reporting of errors to the corresponding...

Страница 296: ...able reporting of the corresponding error in the Port 0 17 Implementation Specific Error Detect Register RW 0 1 TTL_EVENT_EN 1 Enable reporting of the corresponding error in the Port 0 17 Implementati...

Страница 297: ...Implementation Specific Error Detect Register RW 0 20 STOMP_TO_EN 1 Enable reporting of the corresponding error in the Broadcast Port Implementation Specific Error Detect Register RW 0 21 RX_STOMP_EN...

Страница 298: ...mentation Specific Error Detect Register RW 0 31 REORDER_EN 1 Enable reporting of the corresponding error in the Broadcast Port Implementation Specific Error Detect Register RW 0 Lane Base Address 0 0...

Страница 299: ...d is subject to an NDA Integrated Device Technology 25 0x039910 26 0x039A10 27 0x039B10 28 0x039C10 29 0x039D10 30 0x039E10 31 0x039F10 32 0x03A010 33 0x03A110 34 0x03A210 35 0x03A310 36 0x03A410 37 0...

Страница 300: ...d UNUSED BAD_SPEE D_EN LANE_INV ER_DET_E N 24 31 IDLE2_FRA ME_EN Reserved TX_RX_MIS MATCH_EN DESCRAM _SYNC_EN BAD_CHA R_EN LANE_RDY _EN LANE_SYN C_EN Bits Name Description Type Reset Value 0 18 Reserv...

Страница 301: ...EN Bits Name Description Type Reset Value 0 18 Reserved Reserved RO 0 19 21 UNUSED Reserved RW 0 22 BAD_SPEED_EN 1 Enable reporting of the corresponding error in the Lane 0 47 Error Detect Register RW...

Страница 302: ...acket Generation and Capture Registers For more information on how to use these registers see Packet Generation and Capture 10 11 1 Packet Generation and Capture Base Addresses Port Address 0 0x100100...

Страница 303: ...s ready to be read from the destination port s Final Buffer RO 0 17 EN 1 Enable data structure access for internal data structure Write access for the Start port Read access for End port RW 0 18 END_P...

Страница 304: ...ter For base address information see Packet Generation and Capture Base Addresses Register Name PORT_ 0 17 _PGC_DATA Reset Value 0x0000_0000 Register Offset 0x100104 0x10 port_num Bits 0 1 2 3 4 5 6 7...

Страница 305: ...The per port versions of these registers are port specific 10 12 1 Base Addresses for IDT Specific Routing Table Registers Port Device Table Base Address Domain Table Base Address Broadcast 0xE00000...

Страница 306: ...EV_RTE_TABLE_ 0 255 Reset Value 0x0000_00DE Register Offset 0xE00000 0x4 DestID Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 PORT Bits Name Description Type Reset Value 0 23...

Страница 307: ...register is Port 0 17 Domain Routing Table Register 0 255 Register Name BCAST_DOM_RTE_TABLE_ 0 255 Reset Value 0x0000_00DE Register Offset 0xE00400 0x4 DestID Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 1...

Страница 308: ...e Register 0 255 Register Name PORT_ 0 17 _DEV_RTE_TABLE_ 0 255 Reset Value 0x0000_00DE Register Offset 0xE10000 0x1000 port_num 0x4 DestID Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Res...

Страница 309: ...this register is Port 0 17 Domain Routing Table Register 0 255 Register Name PORT_ 0 17 _DOM_RTE_TABLE_ 0 255 Reset Value 0x0000_00DE Register Offset 0xE10400 0x1000 port_num 0x4 Domain Bits 0 1 2 3 4...

Страница 310: ...ated Device Technology 10 13 Trace Comparison Values and Masks Registers 10 13 1 Base Addresses for Trace Comparison Values and Masks Registers Port Offset Address 0 0xE40000 1 0xE40100 2 0xE40200 3 0...

Страница 311: ...7 VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is c...

Страница 312: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31 i...

Страница 313: ...ALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compa...

Страница 314: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd comparison bit Bit 31 is a...

Страница 315: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 316: ...07 VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is...

Страница 317: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 318: ...VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is comp...

Страница 319: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd comparison bit Bit 31 is a...

Страница 320: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 321: ...07 VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is...

Страница 322: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 323: ...VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is com...

Страница 324: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd comparison bit Bit 31 is a...

Страница 325: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 326: ...07 VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is...

Страница 327: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 328: ...VALUE 08 15 VALUE 16 23 VALUE 24 31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is com...

Страница 329: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd comparison bit Bit 31 is a...

Страница 330: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 331: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is compared to the 1st packet bit Bit 31...

Страница 332: ...31 VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 3...

Страница 333: ...LUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 129th packet bit Bit 31 is...

Страница 334: ...SK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd packet comparison bit Bit 31...

Страница 335: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 336: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is compared to the first packet bit Bit 31...

Страница 337: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 338: ...E Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 129th packet bit Bit 31 is c...

Страница 339: ...SK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd packet comparison bit Bit 31...

Страница 340: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 341: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is compared to the 1st packet bit Bit 31...

Страница 342: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 343: ...LUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 129th packet bit Bit 31 is...

Страница 344: ...SK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd packet comparison bit Bit 31...

Страница 345: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 346: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the first 32 bits received in the packet Bit 0 is compared to the first packet bit Bit 31...

Страница 347: ...VALUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 65th packet bit Bit 31...

Страница 348: ...LUE Bits Name Description Type Reset Value 0 31 VALUE This value is used for a bit by bit comparison against the next 32 bits received in the packet Bit 0 is compared to the 129th packet bit Bit 31 is...

Страница 349: ...SK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 33rd packet comparison bit Bit 31...

Страница 350: ...MASK Bits Name Description Type Reset Value 0 31 MASK This value is used for a bit by bit mask against the next 32 bits of the comparison value Bit 0 is a mask for the 97th comparison bit Bit 31 is a...

Страница 351: ...d 24 31 Reserved TRACE_OUT_PORT PORT_RST _CTL Bits Name Description Type Reset Value 0 Reserved Reserved RO 0 1 FATAL_ERR_PKT_ MGT Action to take when Port 0 17 Error and Status CSR PORT_ERR is set 0...

Страница 352: ...56 25 MHz 1 Internal system clock is 312 5 MHz Note The reset value of this field is determined by the setting of the FSEL0 pin RO Undefined 19 CUT_THRU_EN Controls transfer mode from the Input Buffer...

Страница 353: ...ription Type Reset Value 0 27 Reserved Reserved RO 0 28 CFG_PW_PEND 1 The Configuration Block has encountered a condition that required it to initiate a port write Once set this bit remains set until...

Страница 354: ...vice s JTAG and or I2C logic Register Name AUX_PORT_ERR_RPT_EN Reset Value 0x0000_0000 Register Offset 0xF20018 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved I2C_LOG...

Страница 355: ...s domain Register Name RIO_DOMAIN Reset Value 0x0000_0000 Register Offset 0xF20020 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 DOMAIN Bits Name Description Type Reset Valu...

Страница 356: ...erved Bits Name Description Type Reset Value 0 7 SRCID_MSB Most significant byte of the sourceID to be used for all port writes The size of the sourceID is determined by Port Write Target deviceID CSR...

Страница 357: ...0000_0000 Register Offset 0xF2002C Bits 0 1 2 3 4 5 6 7 00 07 ASSY 08 15 ASSY 16 23 VENDOR 24 31 VENDOR Bits Name Description Type Reset Value 0 15 ASSY This value is assigned to the ASSY field in the...

Страница 358: ...eset Value 0 31 SOFT_RESET 0x00030097 Reset the device for more information see Resets after Power Up WO 0 Register Name I2C_MASTER_CTL Reset Value Undefined Register Offset 0xF20050 Bits 0 1 2 3 4 5...

Страница 359: ...ster Frequency Select 0 400 kHz Fast mode 1 100 kHz Standard mode RW 0 7 8 Reserved Reserved RO 0 9 15 CLK_DIV Internal use only Do not write to this field RW 0x62 16 19 Reserved Reserved RO 0 20 CHKS...

Страница 360: ...6 WORD_ERR_22BI T 1 22 bits of read data were expected but the operation was terminated prematurely Reset on read RR 0 7 WORD_ERR_32BI T 1 32 bits of read data were expected but the operation was ter...

Страница 361: ...5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved JTAG_INT_ EN JTAG_PW_ EN JTAG_PW_ PEND Bits Name Description Type Reset Value 0 28 Reserved Reserved RO 0 29 JTAG_INT_EN 0 Disable JTA...

Страница 362: ...0x0000_00FF Register Offset 0xF20060 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 TRIG_CNT Bits Name Description Type Reset Value 0 23 Reserved Reserved RO 0 24 31 TRIG_CNT...

Страница 363: ...ive first no need to reserve for lower priority However if lower priority packet arrive first they cannot use all the buffers if there are no higher priority packets that are currently in the buffer I...

Страница 364: ...und robin only mode proportional fairness is disabled RW 0b000 18 26 OUTPUT_CREDIT _RSVN Default bandwidth reservation value all ports for the output scheduler algorithm This value must be less than t...

Страница 365: ...on another the OUTPUT_CREDIT_MIN MAX values in this register should be increased to greater than 2000 0x7D0 Register Name SWITCH_PARAM_2 Reset Value 0x03E8_03E8 Register Offset 0xF2006C Bits 0 1 2 3 4...

Страница 366: ...Undefined Register Offset 0xF20200 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 QUAD3_CFG QUAD2_CFG QUAD1_CFG QUAD0_CFG Bits Name Description Type Reset Value 0 23 Reserved...

Страница 367: ...d is subject to an NDA Integrated Device Technology 30 31 QUAD0_CFG 0b00 3 by 4x ports 0b01 2 by 4x 2 by 2x ports 0b10 1 by 4x 4 by 2x ports 0b11 2 by 4x 1 by 2x 2 by 1x ports Note The initial value o...

Страница 368: ...specific ports and PLLs is performed PLL_SEL and PORT_SEL are active for this setting 1 Reset all device level digital logic global reset except for the configuration registers is performed This inclu...

Страница 369: ...by bits in this field that are set to 1 are reset Bit 14 Port 17 Bit 15 Port 16 Bit 31 Port 0 Note The main use of this field is to initiate resets to specific ports when a modification to the PLL_DI...

Страница 370: ...ister 0 39 Register Name BCAST__MCAST_MASK_ 0 39 Reset Value 0x0000_0000 Register Offset 0xF30000 0x4 multicast_mask_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved PORT_MASK 16 23 PORT_MASK 24...

Страница 371: ...is Broadcast Multicast Mask Register 0 39 Register Name PORT_ 0 17 _MCAST_MASK_ 0 39 Reset Value 0x0000_0000 Register Offset 0xF38000 0x100 port_num 0x4 multicast_mask_num Bits 0 1 2 3 4 5 6 7 00 07...

Страница 372: ...DA Integrated Device Technology 10 16 Port Function Registers 10 16 1 Port 0 17 Function Registers Base Addresses Port Offset Address 0 0xF40000 1 0xF40100 2 0xF40200 3 0xF40300 4 0xF40400 5 0xF40500...

Страница 373: ...24 31 TRACE_P W_EN PORT_LO G_EN LANE_LOG _EN LT_LOG_E N CRC_RETX_LIMIT Reserved Bits Name Description Type Reset Value 0 1 Reserved Reserved RO 0 2 CRC_DIS CRC Check Disable 0 Perform normal packet C...

Страница 374: ...the port that the packet was received on is contrary to the RapidIO Specification Rev 2 1 RW 0 15 FILTER_3_EN 0 Disable filter comparison 3 1 Enable filter RW 0 16 FILTER_2_EN 0 Disable filter compar...

Страница 375: ...vel errors RW 0 26 LANE_LOG_EN 0 Disable error logging for lane level errors 1 Enable error logging for lane level errors RW 0 27 LT_LOG_EN 0 Disable error logging for logical transport errors 1 Enabl...

Страница 376: ...port encountered a condition when the error rate has exceeded the programmed error rate threshold RW 0 1 TTL_EVENT 1 A packet has been stored in the port output buffer for a period of time that excee...

Страница 377: ...disabled RW 0 11 MANY_RETRY 1 The port detected a retry count that triggered a link partner congestion event RW 0 12 RX_DROP 1 Received a non maintenance packet when the reception of non maintenance p...

Страница 378: ...ompleting the transmission of 15 Status control symbols RW 0 27 PORT_WIDTH 1 The maximum configured port width could not be initialized and the port selected a lower lane width RW 0 28 IDLE_IN_PKT 1 A...

Страница 379: ...TE_ISSU E_EN 08 15 Reserved SET_ACKI D_EN TX_DROP_ EN MANY_RE TRY_EN RX_DROP_ EN Reserved BAD_TT_E N SHORT_EN 16 23 UNSOL_RF R_EN FATAL_TO_ EN RETRY_EN RETRY_AC KID_EN STOMP_T O_EN RX_STOM P_EN LR_CMD...

Страница 380: ...17 Implementation Specific Error Detect Register RW 1 16 UNSOL_RFR_EN 1 Enable the capture of the corresponding error in the Port 0 17 Implementation Specific Error Detect Register RW 1 17 FATAL_TO_E...

Страница 381: ...apture of the corresponding error in the Port 0 17 Implementation Specific Error Detect Register RW 1 28 IDLE_IN_PKT_EN 1 Enable the capture of the corresponding error in the Port 0 17 Implementation...

Страница 382: ...ts 0 1 2 3 4 5 6 7 00 07 COUNT 08 15 COUNT 16 23 COUNT 24 31 COUNT Bits Name Description Type Reset Value 0 31 COUNT A saturating count of packet acknowledgements transmitted by the port for VC0 packe...

Страница 383: ...escription Type Reset Value 0 31 COUNT A saturating count of the number of retry symbols transmitted by the port for VC0 packets Note To enable this counter set the Port 0 17 Operations Register CNTRS...

Страница 384: ...Trace counters are incremented for each packet received This implies that retried packets which match the trace criteria will cause the counter to increment Note To enable this counter set the Port 0...

Страница 385: ...Trace counters are incremented for each packet received This implies that retried packets which match the trace criteria will cause the counter to increment Note To enable this counter set the Port 0...

Страница 386: ...tering counters are incremented for each packet received This implies that retried packets which match the filter criteria will cause the counter to increment Note To enable this counter set the Port...

Страница 387: ...tering counters are incremented for each packet received This implies that retried packets which match the filter criteria will cause the counter to increment Note To enable this counter set the Port...

Страница 388: ...08 15 COUNT 16 23 COUNT 24 31 COUNT Bits Name Description Type Reset Value 0 31 COUNT A saturating count of packet acknowledgements received by the port for VC0 packets Note To enable this counter set...

Страница 389: ...0048 0x100 port_num Bits 0 1 2 3 4 5 6 7 00 07 COUNT 08 15 COUNT 16 23 COUNT 24 31 COUNT Bits Name Description Type Reset Value 0 31 COUNT A saturating count of received retry symbols by the port for...

Страница 390: ...31 COUNT Bits Name Description Type Reset Value 0 31 COUNT A saturating count of VC0 packets received by the port Note To enable this counter set the Port 0 17 Operations Register CNTRS_EN bit Revisio...

Страница 391: ...rt Function Registers Register Name PORT_ 0 17 _TRACE_PW_CTL Reset Value 0x0000_0000 Register Offset 0xF40058 0x100 port_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Res...

Страница 392: ...e synchronization state machines Vmin is defined as follows Revision C 0b000 Vmin 127 0b001 Vmin 212 1 0b010 Vmin 213 1 0b011 Vmin 214 1 0b100 Vmin 215 1 0b101 Vmin 216 1 0b110 0b111 Vmin 0 Revision A...

Страница 393: ...ropped by the port s receiver logic Note To be consistent with the RapidIO Specification Rev 2 1 packets are dropped silently when multicast using a port mask value of all 0s no ports selected This co...

Страница 394: ...address information see Port Function Registers Register Name PORT_ 0 17 _VC0_PKT_DROP_TX_CNTR Reset Value 0x0000_0000 Register Offset 0xF40068 0x100 port_num Bits 0 1 2 3 4 5 6 7 00 07 COUNT 08 15 C...

Страница 395: ...3 4 5 6 7 00 07 COUNT 08 15 COUNT 16 23 COUNT 24 31 COUNT Bits Name Description Type Reset Value 0 31 COUNT A saturating count of VC0 packets that have been dropped by the port s transmit logic becaus...

Страница 396: ...Port 0 17 Congestion Retry Counter Register Register Name PORT_ 0 17 _RETRY_CNTR Reset Value 0xFFFF_0000 Register Offset 0xF400CC 0x100 port_num Bits 0 1 2 3 4 5 6 7 00 07 RETRY_LIM 08 15 RETRY_LIM 1...

Страница 397: ...000_0000 Register Offset 0xF400F0 0x100 port_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved CLR_MAN Y_RETRY RETRY_LI M_EN RX_FC Bits Name Description Type Reset V...

Страница 398: ...Reserved RO 0 2 CRC_DIS 0 Perform normal packet CRC 1 Packet CRC check reports valid CRC regardless of condition WO 0 3 PORT_INT_EN 0 Do not generate interrupt if an error is detected 1 Generate inter...

Страница 399: ...comparison 0 1 Enable filter WO 0 19 TRACE_3_EN 0 Disable TC Value 3 1 Enable TC Value 3 WO 0 20 TRACE_2_EN 0 Disable TC Value 2 1 Enable TC Value 2 WO 0 21 TRACE_1_EN 0 Disable TC Value 1 1 Enable T...

Страница 400: ...ion Registers CPS 1848 User Manual 400 June 2 2014 Formal Status This document is confidential and is subject to an NDA Integrated Device Technology 31 Reserved Reserved RO 0 Continued Bits Name Descr...

Страница 401: ...ror rate has exceeded the programmed error rate threshold RW 0 1 TTL_EVENT 1 A packet has been stored in the port output buffer for a period of time that exceeds the time to live timeout value This al...

Страница 402: ..._DROP 1 The port dropped a non maintenance packet when the transmission of non maintenance packets was disabled RW 0 11 MANY_RETRY 1 The port detected a retry count that triggered a link partner conge...

Страница 403: ...RT_INIT 1 Indicates that port initialization acquired after completing the transmission of 15 Status control symbols RW 0 27 PORT_WIDTH 1 The maximum configured port width could not be initialized and...

Страница 404: ...SHORT_E N 16 23 UNSOL_RF R_EN FATAL_TO_ EN RETRY_EN RETRY_AC KID_EN STOMP_T O_EN RX_STOM P_EN LR_CMD_E N LR_X2_EN 24 31 UNEXP_E OP_EN UNEXP_ST OMP_EN PORT_INIT _EN PORT_WID TH_EN IDLE_IN_P KT_EN LOA_...

Страница 405: ...17 Implementation Specific Error Detect Register RW 0 17 FATAL_TO_EN 1 Enable the capture of the corresponding event in the Port 0 17 Implementation Specific Error Detect Register RW 0 18 RETRY_EN 1 E...

Страница 406: ...ecific Error Detect Register RW 0 28 IDLE_IN_PKT_EN 1 Enable the capture of the corresponding event in the Port 0 17 Implementation Specific Error Detect Register RW 0 29 LOA_EN 1 Enable the capture o...

Страница 407: ...X_STOP ALL_FLAG _STOP Bits Name Description Type Reset Value 0 28 Reserved Reserved RO 0 29 LOG_TBL_OVER WRITE 0 Discard further errors when the error log is full 1 Overwrite the error log with new e...

Страница 408: ...0x0000_0000 Register Offset 0xFD0004 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved ERR_SOURCE 24 31 ERR_GROUP ERR_NUM Bits Name Description Type Reset Value 0 16 Reserved Reserved...

Страница 409: ...Reserved Reserved RO 0 9 ERR_SOURCE_M ASK 0 Compare the error source 1 Do not compare the error source RW 0 10 ERR_GROUP_MA SK 0 Compare the error group 1 Do not compare the error group RW 0 11 ERR_NU...

Страница 410: ...ster RR 0 26 FLAG_ERR_5 Asserted to indicate an error applies to Register 5 in Error Log Match Register 0 7 This field can be reset by FLAG_RESET in the Error Log Control 2 Register RR 0 27 FLAG_ERR_4...

Страница 411: ...e 0x0000_0000 Register Offset 0xFD002C Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 CNT 24 31 CNT Bits Name Description Type Reset Value 0 15 Reserved Reserved RO 0 16 31 CNT Error log eve...

Страница 412: ...Reserved Reserved RO 0 26 STOP_EM 0 Enable error management 1 Stop error management Disable all IDT maintenance packet port writes including those resulting from trace matches Note When set to 1 it do...

Страница 413: ...cument is confidential and is subject to an NDA Integrated Device Technology 10 19 PLL Registers 10 19 1 PLL Register Base Addresses PLL Domain Address 0 0xFF0000 1 0xFF0010 2 0xFF0020 3 0xFF0030 4 0x...

Страница 414: ...gister Name PLL_ 0 11 _CTL_1 Reset Value Undefined Register Offset 0xFF0000 0x10 pll_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved PLL_PWR_ DOWN PLL_DIV_S EL Bit...

Страница 415: ...base address information see PLL Registers Register Name PLL_ 0 11 _CTL_2 Reset Value 0x0000_0001 Register Offset 0xFF0004 0x10 pll_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserv...

Страница 416: ...FF0 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved PLL_DIV_S EL Bits Name Description Type Reset Value 0 30 Reserved Reserved RO 0 31 PLL_DIV_SEL Selects 6 25 Gbaud 3...

Страница 417: ...ol Registers 10 20 1 Lane Control Base Addresses Lane Address 0 0xFF8000 1 0xFF8100 2 0xFF8200 3 0xFF8300 4 0xFF8400 5 0xFF8500 6 0xFF8600 7 0xFF8700 8 0xFF8800 9 0xFF8900 10 0xFF8A00 11 0xFF8B00 12 0...

Страница 418: ...tial and is subject to an NDA Integrated Device Technology 28 0xFF9C00 29 0xFF9D00 30 0xFF9E00 31 0xFF9F00 32 0xFFA000 33 0xFFA100 34 0xFFA200 35 0xFFA300 36 0xFFA400 37 0xFFA500 38 0xFFA600 39 0xFFA7...

Страница 419: ...A IN PRBS_EN XMITPRBS PRBS_RX_ CHECKER _MODE Reserved 16 23 LPBK_10BI T_EN LPBK_8BIT _EN Reserved TX_SYMBOL_CTL TX_AMP_CTL 24 31 TX_AMP_CTL TX_RATE RX_RATE LANE_DIS Bits Name Description Type Reset Va...

Страница 420: ...ate port write on error detect RW 0 11 PRBS_TRAIN PRBS RX training mode 0 Disable 1 Enable Note Errors are not reported when in training mode RW 0 12 PRBS_EN Enable load of initial PRBS seed from CSR...

Страница 421: ...ote To enable write access to this field set AMP_PROG_EN to 1 in the Lane 0 47 Status 3 CSR RW 0b110100 27 28 TX_RATE These bits in conjunction with the PLL_DIV_SEL bit in the PLL 0 11 Control 1 Regis...

Страница 422: ...is a programming error to set the value of this field differently from the value of TX_RATE Note The initial value of this field is determined by the setting of the SPD 1 0 external pins Note Before...

Страница 423: ...0xFF8004 0x100 lane_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved PRBS_SEED 08 15 PRBS_SEED 16 23 PRBS_SEED 24 31 PRBS_SEED Bits Name Description Type Reset Value 0 Reserved Reserved RO 0 1 31 PRBS_SEED Se...

Страница 424: ...RBS Error Counter Register Register Name LANE_ 0 47 _PRBS_ERR_CNTR Reset Value 0x0000_0000 Register Offset 0xFF8008 0x100 lane_num Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved PRB...

Страница 425: ...erved Reserved RO 0 19 21 UNUSED Reserved RW 0 22 BAD_SPEED 1 A link speed was requested that is not supported because of the PLL configuration RW 0 23 LANE_INVER_DE T 1 A lane polarity inversion was...

Страница 426: ...E_RDY _EN LANE_SYN C_EN Bits Name Descriptiona Type Reset Value 0 18 Reserved Reserved RO 0 19 21 UNUSED Reserved RW 0 22 BAD_SPEED_EN 0 Disable 1 Enable capturing that a link speed was requested that...

Страница 427: ...d was not in the valid set of characters This could be an illegal special character or a code group with no valid decoding RW 0 30 LANE_RDY_EN 0 Disable 1 Enable capturing that Lane ready was lost but...

Страница 428: ...e Description Type Reset Value 0 2 INFO_TYPE Type of logged information 0b000 Packet 0b001 Reserved 0b010 Short control symbol only Lane 0 47 Data Capture 0 Register is valid 0b011 Long control symbol...

Страница 429: ...gister Name LANE_ 0 47 _DATA_CAPT_0 Reset Value 0x0000_0000 Register Offset 0xFF8018 0x100 lane_num Bits 0 1 2 3 4 5 6 7 00 07 CAPT_DATA 08 15 CAPT_DATA 16 23 CAPT_DATA 24 31 CAPT_DATA Bits Name Descr...

Страница 430: ...le RX DFE Supported combinations include RX_DFE_DIS 1 TAP_x_SEL 0 Received signal is not modified by DFE and coefficient updates cannot be written to the register fields RX_DFE_DIS 1 TAP_x_SEL 1 Coeff...

Страница 431: ...programming error if this bit is set to 0 when RX DFE is enabled RW 0 18 TAP_1_SEL 1 Enable register adjustment of Tap 1 DFE coefficient Note It is a programming error if this bit is set to 0 when RX...

Страница 432: ...eset default value Most significant bit is a sign bit with 1 meaning positive and 0 meaning negative Positive values range from 0b100000 Positive 0 up to 0b111111 31 Negative values range from 0b01111...

Страница 433: ...the coefficient used to adjust the received signal based on the value of the bit received immediately before the current bit Positive values range from 0b000000 0 up to 0b011111 31 Values 0b100000 0b...

Страница 434: ...N LANE_PW_ EN PRBS_TRA IN PRBS_EN XMITPRBS PRBS_RX_ CHECKER _MODE Reserved 16 23 LPBK_10BI T_EN LPBK_8BIT _EN Reserved TX_SYMBOL_CTL TX_AMP_CTL 24 31 TX_AMP_CTL TX_RATE RX_RATE LANE_DIS Bits Name Desc...

Страница 435: ...ite on error detect RW 0 11 PRBS_TRAIN 0 Disable PRBS RX training mode 1 Enable PRBS RX training mode Note Errors are not reported when in training mode RW 0 12 PRBS_EN Enable load of initial PRBS see...

Страница 436: ...ote To enable write access to this field set AMP_PROG_EN to 1 in the Lane 0 47 Status 3 CSR RW 0b110100 27 28 TX_RATE These bits in conjunction with the PLL_DIV_SEL bit in the PLL 0 11 Control 1 Regis...

Страница 437: ...is a programming error to set the value of this field differently from the value of TX_RATE Note The initial value of this field is determined by the setting of the SPD 1 0 external pins Note Before...

Страница 438: ...4 Bits 0 1 2 3 4 5 6 7 00 07 Reserved PRBS_SEED 08 15 PRBS_SEED 16 23 PRBS_SEED 24 31 PRBS_SEED Bits Name Description Type Reset Value 0 Reserved Reserved RO 0 1 31 PRBS_SEED Seed value for PRBS gener...

Страница 439: ...ne polarity inversion was detected and compensated for only reported when correction is applied RW 0 24 IDLE2_FRAME 1 An error was detected with the received IDLE2 frame RW 0 25 26 Reserved Reserved R...

Страница 440: ...C_EN BAD_CHA R_EN LANE_RDY _EN LANE_SYN C_EN Bits Name Descriptiona Type Reset Value 0 18 Reserved Reserved RO 0 19 21 UNUSED Reserved RW 0 22 BAD_SPEED_EN 0 Disable 1 Enable capturing that a link spe...

Страница 441: ...aracters This could be an illegal special character or a code group with no valid decoding RW 0 30 LANE_RDY_EN 0 Disable 1 Enable capturing that Lane ready was lost but sync remained high RW 0 31 LANE...

Страница 442: ...erved RW 0 13 RX_DFE_DIS Revision B and later devices 1 Disable RX DFE Revision A device 1 Enable RX DFE Supported combinations include RX_DFE_DIS 1 TAP_x_SEL 0 Received signal is not modified by DFE...

Страница 443: ...TAP_2_SEL 1 Enable register adjustment of Tap 2 DFE coefficient Note It is a programming error if this bit is set to 0 when RX DFE is enabled RW 0 18 TAP_1_SEL 1 Enable register adjustment of Tap 1 DF...

Страница 444: ...N Bits Name Description Type Reset Value 0 2 Reserved Reserved RO 0 3 8 TAP_OFFSET_CF G Value to load into Offset coefficient For more information see Lane 0 47 DFE 2 Register RW 0 9 11 TAP_4_CFG Valu...

Страница 445: ..._SI ZE Reserved 16 23 IDLE1_ER R Reserved 24 31 Reserved LR_ACKID _ILL PRTCL_ER R Reserved DELIN_ER R CS_ACK_IL L LINK_TIME OUT Bits Name Description Type Reset Value 0 IMP_SPEC_ERR 0 Did not detect a...

Страница 446: ...a link response with an ackID that is not outstanding 1 Detected a link response with an ackID that is not outstanding RW 0 27 PRTCL_ERR 0 Did not detect a protocol error 1 Detected a protocol error R...

Страница 447: ...e Description Type Reset Value 0 IMP_SPEC_ERR_ EN 0 Disable the capture of IDT implementation specific errors 1 Enable the capture of IDT implementation specific errors RW 0 1 8 Reserved Reserved RO 0...

Страница 448: ...a link response with an ackID that is not outstanding RW 0 27 PRTCL_ERR_EN 0 Disable the capture of protocol errors 1 Enable the capture of protocol errors RW 0 28 Reserved Reserved RO 0 29 DELIN_ERR...

Страница 449: ...rial Physical Layer Specification RapidIO Specification Rev 2 1 Part 7 System and Device Interoperability Specification RapidIO Specification Rev 2 1 Part 8 Error Management Extensions Specification R...

Страница 450: ...or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of...

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