IDT CPS-1848, Руководство пользователя

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3. RapidIO Lanes > Lane and Port Speeds
CPS-1848 User Manual 73 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
3.2 Lane and Port Speeds
Each S-RIO port can support all lane rates. CPS-1848 ports that are connected to the same group of four lanes have
restrictions on their possible lane rates. Ports can operate in either of two lane-speed groups:
1. 6.25 Gbaud, 3.125 Gbaud
2. 5.0 Gbaud, 2.5 Gbaud, 1.25 Gbaud
A port’s speed is controlled through changing the speed of the lanes connected to the port. The speeds available are controlled
through the following registers and fields:
• PLL_DIV_SEL field of the
PLL {0..11} Control 1 Register (selection of lane-speed group)
• TX_RATE and RX_RATE fields in the Lane {0..47} Control Register (lane rate from a lane-speed group)
3.2.1 Lane Speed Change Examples
This first example assumes that Quadrant 0 of the CPS-1848 uses a configuration value of 0b01 (see Table 20 ). This connects
port 0 to lanes 0 and 1, and port 12 to lanes 2 and 3. Assume that port 0 and 12 are currently operating at a lane rate of
5 Gbaud. In addition, assume that port 0 should operate at 6.25 Gbaud, and port 12 should operate at 3.125 Gbaud. Changing
the PLL selected for the SerDes affects both ports and requires a per-port reset of both ports. The register accesses listed in
Table 22 are required to reconfigure the lane speeds of the ports.
Each SerDes has a single PLL. The PLL can be configured to operate at 2.5 GHz, supporting the
5.0/2.5/1.25 Gbaud lane speed groups, or at 3.125 GHz, supporting the 6.25/3.125 Gbaud speed
group. Each lane can be configured to support a multiple of the base PLL frequency.
IDT recommends that S-RIO ports be disabled before changing any lane speeds. Ports can be disabled
by setting PORT_DIS to 1 in
Port {0..17} Control 1 CSR . Ports can be enabled after all lane speeds
have been configured by setting PORT_DIS set to 0.
Changing the configuration of a PLL affects all ports and lanes associated with that PLL. All ports and
lanes associated with a PLL require a port reset, as described in
Table 6 .
When changing port speeds from 1.25 Gbaud to 3.125 or 6.25 Gbaud, change RX_RATE and
TX_RATE in the
Lane {0..47} Control Register before changing PLL_DIV_SEL in the PLL {0..11}
Control 1 Register .
When changing port speeds from 3.125 or 6.25 Gbaud to 1.25 Gbaud, change PLL_DIV_SEL in the
PLL {0..11} Control 1 Register before changing RX_RATE and TX_RATE in the Lane {0..47} Control
Register .
Table 22: Changing Lane Speed Group on Ports 0 and 12 – Example 1
Step Offset Mask and Value Description
Change PLL selection 0xFF0000
PLL {0..11} Control 1
Register
0x00000001 Select 6.25/3.125 Speed Group by setting the
PLL_DIV_SEL bit.