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IDT Error Management

Revision 1.5

Integrated Device Technology, Inc.

CPS-16/12/8 User Manual

5 - 3

July 10, 2012

5.1.1.2 JTAG Errors

The JTAG errors shown in the table below are detectable by the device. If JTAG error reporting is enabled
each of the errors defined below will sent to the Error Log when detecting

Ack Error

0x11

This error references an event when an acknowl-
edgement is expected but is not received. This
error can occur in Master or slave mode. If the error
happens in Master mode, the data transfer will be
terminated and the error will be captured. Note that
although a NACK can be used by an external Mas-
ter to terminate a CPS transmission, this event will
not be captured as an error

22 bit Memory
Address incom-
plete error

0x12

This error refers to the condition when an unex-
pected START/STOP is seen before all three bytes
of a memory address are received. This occurs
when the device is in slave mode and being
addressed by the Master I2C device. The memory
address will not be updated, and the write opera-
tion will be aborted.

Unexpected
START/STOP

0x13

This error is captured when as a slave, the device
encounters an unexpected START or STOP. When
this happens during addressing or during a mem-
ory address transfer the operation is aborted.
When this happens after memory address transfer
is complete (but before data transfer is complete)
the memory address counter will be updated, but
the memory access will be aborted.

EPROM check-
sum error

0x14

This error occurs while the device is in Master
mode if the checksum value in the image does not
match the calculated value.

Table 5.3 JTAG Errors and Codes -- Group Number 0x2

Error

Code

Description

Incomplete Write

0x20

Unexpected termination of write data to registers if serial data
input is not 32 bit aligned

Table 5.2 I

2

C Errors and Codes -- Group Number 0x1

Error

Code

Description

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42
43
44
45
46
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Содержание CPS-16

Страница 1: ...July 10 2012 IDT CPS 16 12 8 Central Packet Switch User Manual Revision 1 5 Tit...

Страница 2: ...n request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition o...

Страница 3: ...nts 3 1 3 3 Switch Description 3 2 3 4 Switching Scheduler and Priorities 3 3 3 5 Flow Control and Congestion Management 3 5 4 I2C Interface 4 1 4 1 Overview 4 1 4 2 Master Slave Configuration 4 1 4 3...

Страница 4: ...gisters 10 1 10 1 RapidIO Compliance 10 1 10 2 Register Type Field Definitions 10 1 10 3 Address Map 10 2 10 4 Rapid IO Registers 10 8 10 5 RIO extended feature registeR 10 19 10 6 IDT Specific sRIO E...

Страница 5: ...igure 4 7 Combined Format 4 10 Figure 4 8 Master Addresses a Slave Receiver with 10 bit Address 4 10 Figure 4 9 Master Addresses a Slave Transmitter with 10 bit Address 4 10 Figure 4 10 Combined Forma...

Страница 6: ...enance Response Packet generated by CPS 8 2 Table 8 3 Port Configuration 8 4 Table 8 4 Multicast Mask Register References for Multicast Mask Port CSR Usage 8 6 Table 8 5 Region Select 8 7 Table 8 6 Po...

Страница 7: ...NF_MOD_ERR_REPORT_ENABLE 0xF20014 10 32 Table 10 46 AUXPORT_ERR_REPORT_ENABLE 0xF20018 10 33 Table 10 47 MAINT_ERR_REPORT_ENABLE 0xF2001C 10 33 Table 10 48 RIO_DOMAIN 0xF20020 10 33 Table 10 49 RIO_PO...

Страница 8: ...ECIAL_ERR_0 0xFD0008 10 48 Table 10 78 ERR_FLAG 0xFD0028 10 50 Table 10 79 ERR_COUNTER 0xFD002C 10 50 Table 10 80 ERR_RESET 0xFD0030 10 51 Table 10 81 QUAD_CTRL Control Register Map 10 52 Table 10 82...

Страница 9: ...nd responding to error reports from all of the functional blocks within the device Chapter 6 JTAG Boundary Scan describes the CPS JTAG interface and code Chapter 7 Reference Clock describes the refere...

Страница 10: ...read but not modified A sticky bit is a bit that remains set after being set by hardware until a zero is written to it Writing a one to a sticky has no effect on its value A zero field in a register...

Страница 11: ...O specifi cations In addition the device supports lane grouping in an enhanced mode such that a group of 4 Lanes can be configured as four individual non redundant 1x ports The CPS device supports the...

Страница 12: ...st control symbol Support Broadcast 10 Multicast mask Per port independent routing table Packet Trace Each Port provides the ability to match the first 160 bits of any packet against up to four progra...

Страница 13: ...G I2C SRIO Quad 0 Logical SRIO SERDES Lane 0 SRIO SERDES Lane 1 SRIO SERDES Lane 2 SRIO SERDES Lane 3 SRIO Quad 1 Logical SRIO SERDES Lane 4 SRIO SERDES Lane 5 SRIO SERDES Lane 6 SRIO SERDES Lane 7 SR...

Страница 14: ...r less chain can be done by a fast non blocking switch It s also suitable in processing card since more and more processing is moved from RNC to Node B in the emerging applica tions The CPS provides d...

Страница 15: ...CPS family device provides 16 12 8 sRIO lanes which can be configured into up to 16 12 8 ports The 80KSW0001 provides up to 12 ports 1 7 3 Bandwidth CPS provides a 40 30 20 Gbps bandwidth 1 7 4 PPSc...

Страница 16: ...the ability for each of its four lanes to be used as individual 1x ports 1 lane per port When configured into standard mode the quad is usable as a single 4x port 4 sRIO lanes or as a 1x port When an...

Страница 17: ...apidIO Specifications revision 1 3 2 1 3 Lane Configuration SRIO lane characteristics is configurable via a set of QUAD_n_CTRL registers These characteristics include the following Data Rate Transmitt...

Страница 18: ...control symbol will be transmitted within the packet i e within the boundary of the packet s SOP and EOP until the rest or more of the packet becomes available for transmission Cut Through is disabled...

Страница 19: ...value mask is used as a don t care A don t care value results in an automatic match of the corresponding bits in the programmable value with the corresponding packet data bits When all bits of the pac...

Страница 20: ...routed to the trace port 2 2 2 Trace Output Port Features At any given time the device supports a single Trace enabled output port It can be dynamically defined which output port is enabled for the T...

Страница 21: ...s Packets which meet the trace criteria are routed to the trace port even if the packet destination ID reference in the port s route table indicates no route 2 2 4 Trace Function Dynamic Programmabili...

Страница 22: ...ia had a hop count of 0 The device supports the ability for the packet filtering to be enabled disable at each port individually for each unique comparison value at that port The device provides the a...

Страница 23: ...te it will return to the normal operational state after updating the expected ID value If a packet is being received during this transition it will be dropped without response 2 4 4 3 OUTBOUND ACKID C...

Страница 24: ...with a maximum 2 5Gb s data bandwidth the PVCs connected to that quad supports all 4 ports by granting bandwidth to each port in 32bit word portions It is this time sharing concept that is the origin...

Страница 25: ...r space is 3 maximum size packet for priority 0 2 maximum sized packets for priority 1 and 1 maximum sized packet for priority 2 and 3 but this is subject to change by user The input buffer simply pro...

Страница 26: ...per port Each output buffer can track up to 3 packets given that there is enough buffer space for them The output buffer will only allow new packet in if it has free tracking resources and buffer spac...

Страница 27: ...h reach the port bandwidth then the lower priority packet will continuously hold off until higher priority packet bandwidth drop below the port bandwidth The same rule apples to all ports Also the fol...

Страница 28: ...able even at the cost of occasional packet loss It is implemented by not storing packets in the retransmit buffer In this way if a retry was received because the link partner has a full input buffer o...

Страница 29: ...2 8 will operate one burst read to download all data from EEPROM I2C burst read start address 0xh00 16bit address bit The device supports configuration into temporary Master mode in two ways 1 If an e...

Страница 30: ...rary Master mode the state of the external ADS signal is ignored Once the device completes its configuration sequence successfully or unsuccessfully it reverts to slave mode where the ADS signal will...

Страница 31: ...a 16 bit value that defines the total number of configuration blocks to read 0 7 0x0003 0 7 Second byte of a 16 bit value that defines the total number of configuration blocks to read 8 15 For n confi...

Страница 32: ...do that therefore the standard CRC 16 algorithm will not generate a correct CRC The following algorithm will generate the CRC 16 expected at the end of the EEPROM unsigned short icrc16 unsigned char...

Страница 33: ...i 0 crc i carry serial_data else crc i crc i 1 bit_Pos_Mask 1 for i 15 i 0 i remainder crc i i return remainder 4 3 6 Register Map Example The following is a list of registers to be configured throug...

Страница 34: ...unt 1 0x0005 0x00 0x0006 0x00 0x0007 0x57 Address 0x158 2 0x57 0x0008 0x00 Data for block 1 0x00600000 0x0009 0x06 0x000A 0x00 0x000B 0x00 0x000C 0x08 Start of Block 2 Register count 9 0x000D 0x38 Add...

Страница 35: ...s as a 7 bit addressable device as defined by ID 6 0 0x0017 0x08 Data for address 0xE00020 0x0018 0x09 Data for address 0xE00024 0x0019 0x00 Start of Block 3 Register count 1 0x001A 0x00 Address 0x6c...

Страница 36: ...ds data to the CPS 16 12 8 slave receiver c Master device terminates the transfer 2 CPS 16 12 8 to Master device a Master device addresses the CPS 16 12 8 slave b Master device master receiver receive...

Страница 37: ...ogy Inc CPS 16 12 8 User Manual 4 9 July 10 2012 Figure 4 3 Data Transfer Figure 4 4 Acknowledgment Figure 4 5 Master Addressing a Slave with a 7 bit Address Transfer Direction is Not Changed Figure 4...

Страница 38: ...10 2012 Figure 4 7 Combined Format Figure 4 8 Master Addresses a Slave Receiver with 10 bit Address Figure 4 9 Master Addresses a Slave Transmitter with 10 bit Address Figure 4 10 Combined Format Mast...

Страница 39: ...CPS 16 12 8 will respond accordingly even when the slave address is set to specification reserved address ranges As a slave the CPS 16 12 8 read procedure has the memory address section of the transfe...

Страница 40: ...4 Input Data 23 16 Input Data 15 8 Input Data 7 0 A ACK 73 82 92 55 64 A 1 ACK R W R 1 W 0 Device Address 9 8 1 1 1 1 0 S A Sr repeated START DATA A ACK A ACK DATA DATA A ACK DATA _ A P STOP Output Da...

Страница 41: ...5 64 73 83 Memory Address 23 18 Memory Address 17 10 Memory Address 9 2 27 36 18 SLAVE ADDR A 0 ACK R W 0 S START 9 R 1 W 0 Device Address 6 0 DATA A ACK A ACK DATA DATA A ACK DATA A ACK A ACK DATA DA...

Страница 42: ...supports error reporting capability is defined as an Error Source The device supports the ability for the user to enable and disable the error reporting functionality of each of these sources Regardl...

Страница 43: ...e Error Log This is a 32 bit register which lists the location and type of error Error Source Error Code 14 bits that occurred When this register is read the device returns the first entry in the Erro...

Страница 44: ...all three bytes of a memory address are received This occurs when the device is in slave mode and being addressed by the Master I2C device The memory address will not be updated and the write opera t...

Страница 45: ...s A response packet with an error status will be generated Maintenance Write Size Invalid 0x32 Triggered when a write request maintenance packet has an invalid size i e not 8 16 32 or 64 bytes A respo...

Страница 46: ...multicast masks Reads of invalid values also trigger this error Port config error 0x53 Triggered when a direct write to a route table is attempted with an invalid PORT number A NO_ROUTE will be writt...

Страница 47: ...t 0x62 Triggered when Lane 2 of a given quad has lost sync Reported only when quad_err_report is enabled Lane 3 Sync Lost 0x63 Triggered when Lane 3 of a given quad has lost sync Reported only when qu...

Страница 48: ...lization This error will only be detected when the output side of the port transmitter reacquires the port init signal after having lost it It will not be detected when initialization is first acquire...

Страница 49: ...x90 Triggered when a packet is received which exceeds the RIO length maximum 69 words Reported only when Port error reporting is enabled Invalid transaction type 0x91 Triggered when a packet is receiv...

Страница 50: ...lag bits are de asserted The Error Flag Register will be reset when the Error Management module is reset or the Error Flag bit in Error Reset Register is set 5 1 2 3 Error Interrupt The device provide...

Страница 51: ...STOP_EM bit in the Error Reset Register when the Error Counter value reaches 0xFF thus stopping the Error Manager A maintenance packet is generated and transmitted if this sequence occurs under these...

Страница 52: ...ined in the register RIO_PORT_WRITE_SRCID the size is determined by the value of the LARGE_TRANS field in the RIO_PORT_WRITE_INFO register vi ttype transaction 0b0100 vii rdsize wrsize 0b1011 viii Hop...

Страница 53: ...1 and 1149 6 boundary scan cells are on the same chain No additional control cells are provided for independent selection of negative and or positive terminals of the Tx or Rx pairs 6 2 TEST INSTRUCT...

Страница 54: ...imum to reset the controller To deactivate JTAG TRST is tied low so that the TAP controller remains in a known state at all times All of the other JTAG input pins are internally biased in such a way t...

Страница 55: ...ag_config_addr TDI is not used after the address is shifted in Timing is shown below Figure 6 2 JTAG Read Access 6 6 BOUNDARY SCAN JTAG instructions are provided for the purpose of making all the part...

Страница 56: ...lity when supplied with a reference clock of 156 25 MHz Figure 7 1 Reference Clock Representative Circuit 7 2 PLL The device provides an internal PLL to create the 312 5MHz or half of that internal SY...

Страница 57: ...Inc CPS 16 12 8 User Manual 7 2 July 10 2012 Figure 7 2 Internal PLL Clock Generator System Clock PLL REF_CLK SYS_CLK 312 MHz PHY PLL PHY_CLK 625 MHz Byte_CLK 125 MHz PHY_CLK 1 25 GHz Byte_CLK 250 MH...

Страница 58: ...the CPS functions per the RapidIO specifications as a switch It identifies a Maintenance Packet by decoding the ftype field to be 0b1000 The CPS decodes the RIO defined hop_count field of the Maintena...

Страница 59: ...was 3 then the response will be kept at priority 3 3 destinationID uses the value of the request packet s sourceID field 4 sourceID uses the value of the request packet s destinationID field 5 transa...

Страница 60: ...3 Individual Local Route Tables Access In addition to the ability to globally access the routing tables the CPS provides the user with the ability to write and read each individual port s local route...

Страница 61: ...e table with the lower 8 bits config_destID is forced If the destination ID is only 8 bits CPS uses these 8 bits as a direct address offset into the route table to obtain its forwarding information 8...

Страница 62: ...Specification The Standard Route Configuration destination ID Select CSR specifies the destination ID entry in the switch routing table to access when the Standard Route Configuration Port Select CSR...

Страница 63: ...its 10 multicast mask registers indirectly through use of the Multicast Mask Port CSR the Multicast Associate Select CSR and the Multicast Associate Operation CSR as defined in RapidIO Interconnect Sp...

Страница 64: ...to properly map packets to the proper device construct the user must use the route table values defined below 8 2 7 1 Direct Output Port Mapping Packets are routed directly to output ports in a unica...

Страница 65: ...st Mask Register addresses are supported in the Device Route Table but not in the Domain Route Table 8 2 7 3 Default Route The CPS supports references to its default port in both its Device Route Tabl...

Страница 66: ...s two options that define the behavior of the CPS when this control symbol is received from one of the RIO ports The user can program the ENABLE_PORT_RESET field in CPS_CONTROL register If this bit is...

Страница 67: ...This lockout counter is cleared by a local soft reset event 14 There is a symbol counter in the output side of the port that counts the number of link request reset device control symbols for the por...

Страница 68: ...l lanes will be disabled which will force loss of link with the lane partner This will cause link re negotiation to occur in the same way as if the force_reinit function had been invoked 8 3 3 Reset C...

Страница 69: ...onfiguration of the physical layer of all CPS ports This is key to configuring the device to interface properly to adjacent devices in the system prior to any sRIO bring up and initialization routines...

Страница 70: ...utes in the route table Multiple number of routes can be entered which will be either deleted or inserted If a route can not be added the function is terminated and index of unsuccessful route is retu...

Страница 71: ...9 1 1 RIO Ports After Power Up and after device reset the RIO Port configuration is as defined below Table 9 1 Port Configuration at Power Up Lane Port Mode Port Number CPS 8 0 Enhanced 1x 0 1 Enhance...

Страница 72: ...ation long run short run These registers are programmable through the I2C or JTAG interfaces during system initialization as well 9 4 RIO SYSTEM BRING UP The device supports the system bring up requir...

Страница 73: ...ter as only being applicable to end points 10 1 1 Interpretation of Reserved Register Bits The CPS design is based on the RIO definition for the treatment of reserved register bits to support compat i...

Страница 74: ...000004 DEV_INF_CAR 0x000008 ASSY_IDENT_CAR 0x00000C ASSY_INF_CAR 0x000010 PROC_ELEM_FEAT_CAR 0x000014 SWITCH_PORT_INF_CAR 0x000018 SRC_OP_CAR 0x000030 SW_MCAST_SUP_CAR 0x000034 SW_RTE_TBL_LIM_CAR 0x00...

Страница 75: ...400 Global Domain Route Table 0xE10000 Port 0 Device Route Table 0xE10400 Port 0 Domain Route Table 0xE10000 0x1000 PORT_ NUM Registers start for port PORT_NUM 0xE1F000 Port 15 Domain Route Table 0xE1...

Страница 76: ...e Mask 2 0xE4FF50 Broadcast Trace Comparison Value 3 0xE4FF64 Broadcast Trace Mask 3 0xE4FF78 Broadcast Trace Comparison Value 4 0xE4FF8C Broadcast Trace Mask 4 0xF00000 0xF1FFFF Vendor access only 0x...

Страница 77: ...isters 0xF40000 PORT_0_BUF_SIZE 0xF40004 PORT_0_OPS 0xF40008 PORT_0_ERR_REPORT_ENABLE 0xF4000C PORT_0_SWITCH_BUF_STATUS 0xF40010 PORT_0_ACK_CNTR 0xF40014 PORT_0_NACK_CNTR 0xF40018 Reserved 0xF4001C PO...

Страница 78: ...5_FILTER_MATCH_CNTR_1 0xF40F34 PORT_15_FILTER_MATCH_CNTR_2 0xF40F38 PORT_15_FILTER_MATCH_CNTR_3 0xF40F3C PORT_15_FILTER_MATCH_CNTR_4 0xF4FF00 0xF4FF08 Broadcast to Switchport Registers 0xF4FF00 PORT_B...

Страница 79: ...ERR_RESET 0xFF0000 0xFFF000 Quad Control Registers 0xFF0000 QUAD_0_CTRL 0xFF0004 QUAD_0_ERR_REPORT_EN 0xFF1000 QUAD_1_CTRL 0xFF1004 QUAD_1_ERR_REPORT_EN 0xFF2000 QUAD_2_CTRL 0xFF2004 QUAD_2_ERR_REPOR...

Страница 80: ...Name Type Reset Value Comment 15 0 DEV_VENDOR_IDENT FR 0x0038 Device Vendor Identifier Assigned by the RTA specifically for IDT 31 16 DEV_IDENT FR 0x35B 0x35C 0x35D Specific Device Identifier 0x35B is...

Страница 81: ...entifier This field is used to uniquely identify the manufactur ing vendor of the assembly containing this device 31 16 ASSY_IDENT FR 0x0000 This field uniquely identifies the type of assembly used As...

Страница 82: ...it source and destination IDs 1 enabled 5 CRITICAL_REQUEST_FLOW_SU PPORT FR 0b0 0 Critical Request Flow not sup ported 1 Critical Request Flow is sup ported 6 CRC_ERROR_RECOVERY FR 0b1 0 Suppression o...

Страница 83: ...ay or may not be able to bridge between sRIO and another non sRIO interface 0 No support for bridging to a non sRIO interface Table 10 8 SWITCH_PORT_INF_CAR 0x000014 Bit Field Name Type Reset Value Co...

Страница 84: ...yes 5 ATOMIC_SET FR 0b0 Defines the ability of the device to support an atomic set operation 0 no 1 yes 6 ATOMIC_DECREMENT FR 0b0 Defines the ability of the device to support an atomic decrement oper...

Страница 85: ...nes the ability of the device to support a streaming write operation 0 no 1 yes 14 WRITE FR 0b0 Defines the ability of the device to source a write operation 0 no 1 yes 15 READ FR 0b0 Defines the abil...

Страница 86: ...Ds that are supported 0xFF 256 31 16 Reserved Table 10 12 SW_MULT_INF_CAR 0x000038 Bit Field Name Type Reset Value Comment 15 0 MULTICAST_MASKS FR 0x000A Defines the number of multicast mask that are...

Страница 87: ...0 14 COMPONENT_TAG_CSR 0x00006C Bit Field Name Type Reset Value Comment 31 0 COMPONENT_TAG R W 0x00 Component Tag for this device Table 10 15 STD_RTE_CONF_DESTID_SEL_CSR 0x000070 Bit Field Name Type R...

Страница 88: ...0 CONF_OUT_PORT R W 0x00 Destination value through which all mes sages intended for CON_DESTID are sent 15 8 CONF_OUT_PORT_1 R W 0x00 Destination value through which all mes sages intended for CON_DES...

Страница 89: ...e multicast mask 3 1 Reserved 6 4 MASK_CMD R W 0b000 000 Write to verify 001 Add Port 010 Delete Port 100 Delete All Ports 101 Add all Ports 7 Reserved 15 8 EGRESS_PORT_NUMBER R W 0x00 Defines the por...

Страница 90: ...write to ver ify command 0 no association 1 association present 4 1 Reserved 6 5 ASSOCIATION_COMMAND R W 0b00 Command when register is written 00 Write to Verify 01 Delete Association 11 Add associati...

Страница 91: ...e Address hex Associated Registers 0x000140 0x000144 0x000148 0x000158 0x00015C PORT_0_LINK_MAINT_REQ_CSR PORT_0_LINK_MAINT_RESP _CSr ORT_0_LOCAL_ACKID_CSR PORT_0_ERR_STAT_CSR PORT_0_CTRL_CSR 0x000160...

Страница 92: ...erved 0b101 0b111 Reserved See RIO part 6 table 3 6 rev 1 3 31 3 Reserved Table 10 26 PORT_0_LINK_MAINT_RESP_CSR 0x000144 Bit Field Name Type Reset Value Comment 4 0 LINK_STATUS RO 0b00000 Link status...

Страница 93: ...ets in order to manually implement error recovery 7 5 Reserved 12 8 OUTSTANDING_ACKID R W 0b00000 The output port unacknowledged ackID status The next acknowledge control symbol ackID field that indi...

Страница 94: ...R RO 0b0 Input Error Port is stopped 9 INPUT_ERROR_ENCOUNTERED W1R 0b0 Input Error was encountered 10 INPUT_RETRY RO 0b0 Input Retry Port is stopped 15 11 Reserved 16 OUTPUT_ERROR RO 0b0 Output Error...

Страница 95: ..._ENABLE R W 0b0 Enable the Output port 23 PORT_DISABLE R W 0b0 Port Disable 26 24 PORT_WIDTH_OVERRIDE R W 0b000 000 no override 010 single lane port lane 0 011 single lane port lane 2 Others reserved...

Страница 96: ...Access is for Global Route Table 0b00001 Access is for Port 0 Route Table 0b00010 Access is for Port 1 Route Table 0b00011 Access is for Port 2 Route Table 0b00100 Access is for Port 3 Route Table 0b...

Страница 97: ...0x00 0xE10004 Port0 Device Route Table for Device ID 0x01 0xE103FC Port0 Device Route Table for Device ID 0xFF 0xE10400 Port0 Domain Route Table for Device ID 0x00 0xE10404 Port0 Domain Route Table fo...

Страница 98: ...0 0xE40398 Port 3 Trace Comparison Values and Masks Register 0xE40400 0xE40498 Port 4 Trace Comparison Values and Masks Register 0xE40500 0xE40598 Port 5 Trace Comparison Values and Masks Register 0xE...

Страница 99: ...first 32 bits received in the packet Bit 31 will be compared to the first packet bit Bit 30 will be compared to the second packet bit Bit 0 will be compared to the 32nd packet bit Table 10 35 Port_0_T...

Страница 100: ...n the packet Bit 31 will be compared to the 65th packet bit Bit 30 will be compared to the 66th packet bit Bit 0 will be compared to the 96th packet bit Table 10 37 Port_0_Trace_Value_1_Block_3 0xE400...

Страница 101: ...32 bits received in the packet Bit 31 will be compared to the 129th packet bit Bit 30 will be compared to the 130th packet bit Bit 0 will be compared to the 160th packet bit Table 10 39 Port_0_Mask_Va...

Страница 102: ...ock_2 0xE4001C Bit Field Name Type Reset Value Comment 31 0 MASK_VALUE_1_BLOCK_2 R W 0x00000000 This value will be used for a bit by bit comparison against the first 32 bits received in the packet Bit...

Страница 103: ...130th comparison bit Bit 0 will be a mask for the 160th comparison bit Table 10 44 CPS_CONTROL 0xF2000C Bit Field Name Type Reset Value Comment 0 PORT_RESET_BEHAVIOR R W 0b0 Defines action upon recep...

Страница 104: ...ic and for trace match data 1 Trace Port will only be used for trace match data 19 16 Reserved 20 QUAD_OFF_0 R W 0b0 0 On 1 Off Quad sleep mode for power reduc tion 21 QUAD_OFF_1 R W 0b0 0 On 1 Off Qu...

Страница 105: ...s register is used for the user to define the domain this device belongs to Table 10 46 AUXPORT_ERR_REPORT_ENABLE 0xF20018 Bit Field Name Type Reset Value Comment 0 JTAG_ERR_REPORT_ENABLE R W 0b0 0 Di...

Страница 106: ..._INFO register will apply to the Source_ID as well Table 10 49 RIO_PORT_WRITE_INFO 0xF20024 Bit Field Name Type Reset Value Comment 12 0 Reserved 14 13 PRIO R W 0b00 SRIO Priority to be used for port...

Страница 107: ..._IDENT_CAR 0xF2002C Bit Field Name Type Reset Value Comment 15 0 RIO_ASSY_VENDOR_IDENT R W 0x0000 This value will be assigned to the ASSY_VENDOR_IDENT field in the sRIO ASSY_IDENT_CAR 31 16 RIO_ASSY_I...

Страница 108: ...h EPROM read 1 Do not verify checksum with EPROM read 15 12 Reserved 22 16 CLK_DIVISOR R W 0x62 Value used to convert inter nal Sys_Clks to I2C clocks and derive internal timing parameters This value...

Страница 109: ...r ation is complete and was suc cessful If successful this bit will stay high until the next sequence is initiated 22 I2C_READ_IN_PROGRESS RO 0b0 0 I2C read operation is not in progress 1 I2C read ope...

Страница 110: ...1 indicates that an unexpected I2C start or stop was detected Reset on read 31 28 Reserved Base Address Hex Associated Registers 0xF30000 MULTICAST0 0xF30004 MULTICAST1 0xF30008 MULTICAST2 0xF3000C MU...

Страница 111: ...not included in Multicast group 0 1 Port 6 is included in Multicast group 0 7 MCAST_PORT_7 R W 0b0 0 Port 7 is not included in Multicast group 0 1 Port 7 is included in Multicast group 0 8 MCAST_PORT...

Страница 112: ...ters 0xF40300 0xF4033C Switching Port 3 Registers 0xF40400 0xF4043C Switching Port 4 Registers 0xF40500 0xF4053C Switching Port 5 Registers 0xF40600 0xF4063C Switching Port 6 Registers 0xF40700 0xF407...

Страница 113: ...0010 RIO Priority Level 2 Input Buffer Size 23 20 Reserved 27 24 PRI_3_BUF_SIZE R W 0b0010 RIO Priority Level 3 Input Buffer Size 31 25 Reserved Table 10 60 PORT_0_OPS 0xF40004 Bit Field Name Type Res...

Страница 114: ...race Comparison Value 2 is enabled 11 ENABLE_TRACE_COMPARISON_3 R W 0b0 0 Trace Comparison Value 3 is disabled 1 Trace Comparison Value 3 is enabled 12 ENABLE_TRACE_COMPARISON_4 R W 0b0 0 Trace Compar...

Страница 115: ...me Type Reset Value Comment 0 ERROR_REPORT_ENABLE R W 0b0 0 Disable Error Reporting from this port 1 Enable Error Reporting from this port 1 SWITCH_PORT_ERROR_REPORT_ENABLE R W 0b0 0 Disable error rep...

Страница 116: ...1 Empty 4 PRI_0_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 5 PRI_1_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 6 PRI_2_OUTPUT_BUF_STATUS RO 0b0 0 Not Empty 1 Empty 7 PRI_3_OUTPUT_BUF_STATUS RO 0b0...

Страница 117: ...cknowl edgements issued by port 0 Table 10 65 PORT_0_SW_PKT_CNTR 0xF4001C Bit Field Name Type Reset Value Comment 31 0 SWITCH_PKT_COUNT RR 0x00000000 A saturating count of packets sent for transmissio...

Страница 118: ...s at port 0 that have met the defined trace criteria with comparison Value 3 Table 10 69 PORT_0_TRACE_MATCH_CNTR_4 0xF4002C Bit Field Name Type Reset Value Comment 31 0 TRACE_COUNT_4 RR 0x00000000 A s...

Страница 119: ...t 31 0 FILTER_COUNT_4 RR 0x00000000 A saturating count of packets that have met the defined filter criteria with comparison Value 4 Table 10 74 ERR_CAP_REG 0xFD0000 Bit Field Name Type Reset Value Com...

Страница 120: ...6 bits 31 14 Reserved Base Address Hex Associated Registers 0xFD0008 SPECIAL_ERR_REG_0 0xFD000C SPECIAL_ERR_REG_1 0xFD0010 SPECIAL_ERR_REG_2 0xFD0014 SPECIAL_ERR_REG_3 0xFD0018 SPECIAL_ERR_REG_4 0xFD0...

Страница 121: ...Enable flagging the error 19 COUNT_ENABLE R W 0b0 Enable counting the error 20 ERROR_NUMBER_MASK R W 0b0 0 compare the error number 1 do not compare the error number 21 ERROR_GROUP_MASK R W 0b0 0 com...

Страница 122: ...ndicate and error applies to Special error register 2 3 FLAG_ERROR_3 RR 0b0 Assert this field to indicate and error applies to Special error register 3 4 FLAG_ERROR_4 RR 0b0 Assert this field to indic...

Страница 123: ...0b0 Resets the flag register 2 COUNT_RESET R W 0b0 Resets the error count regis ter 3 ERROR_FIFO_RESET R W 0b0 Reset the error FIFO 4 MAINTENANCE_PACKET_DISABLE R W 0b0 0 generation of the main tenanc...

Страница 124: ...QUAD_3_ERROR_REPORT_EN 0xFFF000 Broadcast To All Quads Register Table 10 82 QUAD_0_CTRL 0xFF0000 Bit Field Name Type Reset Value Comment 1 0 SPEEDSEL R W 0b00 Port Speed Selection Default is set by e...

Страница 125: ...te Port Speed Selection for Lanes 2 and 3 Only active if 16 1 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps Default is set by external pins same as con figuration for Lanes 1 and 2 21 19 LANE23_TCOEFF R W 0b...

Страница 126: ...Enables error reporting on a per quad basis 0 disable 1 enable 31 1 Reserved Table 10 84 QUAD_CTRL_BROADCAST 0xFFF000 Bit Field Name Type Reset Value Comment 1 0 SPEEDSEL W 0b00 Port Speed Selection d...

Страница 127: ...ort Speed Selection for Lanes 2 and 3 Only active if 16 1 00 1 25 Gbps 01 2 5 Gbps 10 3 125 Gbps Default is set by external pins same as configuration for Lanes 1 and 2 21 19 LANE23_TCOEFF R W 0b000 S...

Страница 128: ...1x 4x LP Serial Specification Rev 1 3 5 RapidIO Interconnect Specification Part 7 System and Device Inter operability Specification Rev 1 3 6 RapidIO Interconnect Specification Part 9 Flow Control Log...

Страница 129: ...ed including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others Th...

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