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©2018 Integrated Device Technology, Inc.

May 17, 2018

9FGV1006 PhiClock™ PCIe Evaluation Board User Guide

Figure 3.  SMA Connectors Circuit

The circuit is designed for maximum flexibility when testing all possible logic types. Default assembly uses a 0.1

μ

F capacitor in place of 

R14 and R16, and the short across R14 and R16 is cut. No other devices are assembled. This simple AC-coupled configuration allows for 
testing phase noise and jitter of all possible logic types. The circuit can be modified for custom tests. TP3 is a position to place a 
differential FET probe.

Operating Instructions

1. Set all jumpers for power supply choices (E1–E6), interface choices (JP1 and JP2), and set the U2 switches.
2. Connect an interface: USB or I

2

C.

3. In the case of an I

2

C interface, also connect external power supply to jacks J3, J4 and J5.

4. Start Timing Commander for either USB or Aardvark.

a. Start new configuration or load TCS file for existing configuration.

b. Choose PhiClock personality.

c. For Aardvark, click 

 to select Aardvark “Connection Interface”.

d. For a new configuration, prepare all settings.

e. Click 

to connect to the 9FGV1006 device. Top right should turn green. 

f. Click 

to write all settings to the 9FGV1006 device.

g. It should now be possible to measure clocks on outputs.

h. While connected, each change to the settings will be written to the 9FGV1006 immediately and can be observed at the clock outputs.

Содержание 9FGV1006

Страница 1: ...he device can be configured and programmed to generate different combinations of frequencies This evaluation board is designed for differential outputs It can not be used for single ended outputs Boar...

Страница 2: ...Commander The board can be powered from the USB port 3 Output Power Supply Jack J3 Connect to 1 8V 2 5V or 3 3V for the output voltage of the device 4 Core Power Supply Jack J4 Connect to 1 8V 2 5V or...

Страница 3: ...urned with multiple configurations JP1 and JP2 can be applied in JP3 position respectively Connect JP3 SEL_I2C to VDDO and power up the 9FGV1006 in Hardware Select mode This enables changing between 4...

Страница 4: ...l jumpers for power supply choices E1 E6 interface choices JP1 and JP2 and set the U2 switches 2 Connect an interface USB or I2 C 3 In the case of an I2C interface also connect external power supply t...

Страница 5: ...5 2018 Integrated Device Technology Inc May 17 2018 9FGV1006 PhiClock PCIe Evaluation Board User Guide Schematics Figure 4 9FGV1006 PCIe Evaluation Board Schematic page 1...

Страница 6: ...6 2018 Integrated Device Technology Inc May 17 2018 9FGV1006 PhiClock PCIe Evaluation Board User Guide Figure 5 9FGV1006 PCIe Evaluation Board Schematic page 2...

Страница 7: ...7 2018 Integrated Device Technology Inc May 17 2018 9FGV1006 PhiClock PCIe Evaluation Board User Guide Figure 6 9FGV1006 PCIe Evaluation Board Schematic page 3...

Страница 8: ...8 2018 Integrated Device Technology Inc May 17 2018 9FGV1006 PhiClock PCIe Evaluation Board User Guide Figure 7 9FGV1006 PCIe Evaluation Board Schematic page 4...

Страница 9: ...where the failure or malfunction of an IDT product can be rea sonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own...

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