IDT 9FGV1005, Руководство по программированию, Страница: 6 / 10

6 ©2018 Integrated Device Technology, Inc. March 7, 2018
9FGV1005 Register Descriptions and Programming Guide
14 0x0E
7 1 Crystal oscillator LDO: 0 = Disabled, 1 = Enabled.
6 0 Reserved.
[5..0] 000000
Crystal oscillator X1 pin capacitance: Cap (pF) = 7.98 + 0.442 × Bits[5..0].
See section
Crystal Load Capacitance Registers for crystal oscillator load
capacitance configuration.
15 0x0F
7 1 Crystal oscillator circuit: 0 = Disabled, 1 = Enabled.
6 0 Reserved.
[5..0] 000000 Crystal oscillator X2 pin capacitance: Cap (pF) = 7.98 + 0.442 × Bits[5..0].
16 0x10 [7..0] 83-hex Reserved.
17 0x11 [7..0] 1A-hex Reserved.
18 0x12 [7..0] 0C-hex Reserved.
19 0x13 [7..0] 80-hex Reserved.
20 0x14 [7..0] 00-hex Reserved.
21 0x15 [7..0] 02-hex Reserved.
22 0x16 [7..0] 96-hex Reserved.
23 0x17 [7..0] 00-hex Reserved.
24 0x18 [7..0] 00-hex Reserved.
25 0x19 [7..0] 00-hex Reserved.
26 0x1A
7 1
PLL, VCO band calibration start. Toggle to 0 and back to 1 to trigger a
calibration.
The calibration engages at the moment the bit moves from 0 to 1. The
calibration finds the optimum VCO band for the current VCO frequency.
6 0
Override VCO band: 0 = use calibrated VCO band, 1 = use VCO band value
in bits [5..0].
[5..0] 100000 VCO band value. See bit 6.
27 0x1B
7 1 Enable VCO: 0 = VCO disabled, 1 = VCO enabled.
6 1 Enable charge pump: 0 = CP disabled, 1 = CP enabled.
5 1 Enable PLL bias: 0 = PLL bias disabled, 1 = PLL bias enabled.
4 1 Bypass 3
rd
pole in loop filter: 0 = Use 3
rd
pole, 1 = 3
rd
pole bypassed.
[3..0] 1100 Reserved.
28 0x1C
[7..4] 1010 Loop filter R-zero value.
[3..0] 1111 Reserved.
29 0x1D [7..0] 00-hex Reserved.
Table 3. RAM Register Map (Cont.)
Register Address
Register Bit Default Function Description
Decimal Hex