IDT 89HPES24N3A, Руководство пользователя

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IDT Theory of Operation
PES24N3A User Manual 3 - 3 April 10, 2008
Notes
If the ingress link width is less than the egress link width, then an entire TLP must be received before it
can be transmitted on the switch egress port. This is necessary since once a TLP transmission begins, it
must complete uninterrupted at the rate of the egress port. Thus, when the negotiated ingress link width is
less than the egress link width, the PES8T5 operates in a store and forward manner. Ingress TLPs are
queued in the IFB until the entire TLP has been received.
Switch Core
A simplified view of the switch core is shown in Figure 3.1. The switch core consists of two buses. The
primary purpose of the Upstream Bus (U-Bus) is to route TLPs received on a downstream port to the
upstream port while the primary purpose of the Downstream Bus (D-Bus) is route TLPs received on the
upstream port to a downstream port.
To facilitate peer-to-peer transactions, a bus decoupler is provided to link the U-Bus to the D-Bus. In
addition to providing a data path between the U-Bus and the D-Bus, the bus decoupler provides adequate
buffering to accommodate one maximum-sized TLP to allow the U-Bus and D-Bus to operate indepen-
dently. Thus, the transfer from a downstream port to bus decoupler is independent of the transfer from the
bus decoupler to a downstream port. While it may appear that the bus decoupler introduces a store-and-
forward architecture for peer-to-peer transfers, this is not the case. Transactions flowing through the bus
decoupler may be cut-through and typically add no more than five clock cycles of latency.
Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath
In addition to transactions between the upstream port and downstream port and peer-to-peer transac-
tions, the switch core is responsible for routing of transactions which are destined to the same stack on
which the TLP was received. These transactions are referred to as route-to-self.
Ingress to Egress Latency (ns)
x8 to x8 184
x8 to x4 184
x8 to x1 184
x4 to x4 204
x4 to x1 204
x1 to x1 272
Table 3.4 Latency
Downstream
Port
4
Downstream
Port
2
Upstream
Port
0
Bus Decoupler
Queue
U-Bus
D-Bus