IDT 89EBPES16NT2, Руководство пользователя

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IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 6 November 13, 2007
Notes
The PES16NT2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter-
face. The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all
software-visible registers. The Master SMBus interface provides connection to the external serial
EEPROMs used for initialization.
SMBus Slave Interface
On the PES16NT2 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.6.
Note: The SMBus signals to the PCI Express edge connector is disabled by default. To enable
them, place 0-ohm resistors at locations R74 and R75.
.
A fixed slave SMBus address ( 0b1110_111) specified by the SSMBADDR[5,3:1] pins is used.
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
– Byte and Word Write/Read
– Block Write/Read
SMBus Master Interface
The seven bits address for the selected EEPROM device is
0b1010_000
by default.
Slave SMBus Interface Connector
J10
Pin Signal
1 N/C
2 SCL
3 GND
4 SDA
Table 2.6 Slave SMBus Interface Connector
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
4 0
5 SSMBUSADDR[5]
6 1
7 1
Table 2.7 SMBus Slave Interface Address Configuration