IDT 89EBPES16NT2, Руководство пользователя

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IDT Installation of the EB16NT2 Eval Board
EB16NT2 Eval Board Manual 2 - 2 November 13, 2007
Notes
port and an NTB downstream port. The PES16NT2 is a part of the IDT PCIe System Interconnect
Products family and is intended to be used with IDT PCIe System Interconnect Switches. Together, the
chipset targets multi-host and intelligent I/O applications such as communications, storage, and blade serv-
ers, where inter-domain communication is required.
The EB16NT2 non-transparent port is accessible through x8 PCI Express cable connectors.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x8 configuration through a PCI Express
x8 slot.
– A secondary remote system with a PCI Express root complex supporting x8 configuration through
a PCI Express x8 slot.
Reference Clocks
The PES16NT2 requires a pair of differential reference clocks. The EB16NT2 derives these clocks from
a common source which is user-selectable. The common source can be either the host system’s reference
clock or the onboard clock generator. Selection is made by stuffing resistors described in Table 2.1. Typical
usage model for the EB16NT2 in non-transparent mode includes two root complexes: one connects to the
upstream port and the other connects to a NTB port. Each root complex most likely will have its own clock
source. SSC (Spread Spectrum Clock) must be disabled in this configuration.
The source for the onboard clock is the ICS557-03 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB16NT2 allows selection between multiple
clock rates via DIP switches as described in Table 2.2.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.3. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Clock Configuration Stuffing Option
W7 and W8 Clock Source
Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection
Clock Frequency Switch - S2[2:1]
S2[2] S2[1] Clock Frequency
OFF OFF Reserved
OFF ON 125 MHz
ON OFF 100 MHz (Default)
ON ON <Reserved>
Table 2.2 Clock Frequency Selection
Onboard Reference Clock Output (Differential) – J2, J3
J2 Positive Reference Clock
J3 Negative Reference Clock
Table 2.3 SMA Connectors - Onboard Reference Clock