5
CHAPTER 5. SVGA SETUP ............................ 42
5.1
I
NTRODUCTION
.................................................. 42
5.2
F
URTHER
I
NFORMATION
........................................ 43
CHAPTER 6.
PCI BUS ETHERNET INTERFACE .................. 44
APPENDIX A. WATCHDOG TIMER ................ 45
APPENDIX B. I/O ADDRESS MAP ................ 48
B.1
S
YSTEM
I/O
A
DDRESS
M
AP
........................................ 48
B.2
DMA
CHANNEL ASSIGNMENTS
..................................... 49
B.3
I
NTERRUPT ASSIGNMENTS
.......................................... 49
B.4
1
ST
MB
MEMORY MAP
............................................... 50
Содержание WAFER-5823
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