LCD-Kit01A 9
CN1: Panel Signal from CPU board (reference)
Signal Name
Pin #
Pin #
Signal Name
VPCLK 1 2 P33
P34 3 4 P31
P35 5 6 P32
P30 7 8 P28
P29 9 10 P27
P25 11 12 P26
P24 13 14 P21
P23 15 16 P22
P16 17 18 P20
P17 19 20 P18
P19 21 22 P14
P13 23 24 P12
P15 25 26 P11
P7 27 28 P10
PLCD 29 30 PLCD
P9 31 32 P8
P4 33 34 P6
P3 35 36 P5
P2 37 38 P1
M 39
40 P0
SHFCLK 41 42 ENABKL
FPVDD 43 44 FLM
FPVEE 45 46 LP
GND 47 48 GND
+12V 49 50 +12V
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1
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50
LCD-Kit01A 10
SHFCLK:
Shift Clock. Pixel clock for flat panel data.
FLM:
First Line Marker.Flat Panel equivalent of VSYNC.
LP:
Latch Pulse(may also be called CL1).
M:
M signal for panel AC drive control (may also be called
ACDCLK).
ENABKL:
power sequencing control for enabling the backlight
FPVEE:
Power sequencing control for panel bias voltage VEE. May
also be configured as ENABKL
CN2 : DF9-31P Panel interface
Pin#
1 2 3 4 5 6
Signalname
GND
SHFCLK
LP
FLM
GND
P18
Pin#
7 8 9 10 11 12
Signalname
P19
P20
P21
P22 P23
GND
Pin#
13 14 15 16 17 18
Signalname
P10
P11
P12
P13 P14
P15
Pin#
19 20 21 22 23 24
Signalname
GND
P2
P3
P4 P5
P6
Pin#
25 26 27 28 29 30
Signalname
P7
GND
M
PLCD
PLCD
N.C
Pin#
31
Signalname
N.C.
CN4 :Power Connector for backlight inverter
1 +12V
2 FPBACK
3 GND
1
4
4 VR
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