ICP DAS USA PIO-D48, Руководство пользователя, Страница: 14 / 54

PIO-D48 Series Card
48-channel OPTO-22 Compatible DIO Board
User Manual/Ver. 3.4/Aug. 2015/PMH-006-34/Page: 13
Disable\
Clock
Input
D/O Latch CKT
I/O Select (Sec. 6.3.7)
RESET\ (Sec. 6.3.1)
D/I/O
Data
Sec. 6.3.8
Disable
Clock
Input
D/I Buffer CKT
Data
Sec. 6.3.8
Input
Latch
Buffer Input
1 2 3
10 K
GND Vcc
(Pull-high)
(Pull-Low)
JP2/3/4/5/6/7 pull-high/pull-low select
(Default: all JPx are in 2-3 short, selection pull-low)
2.6 D/I/O Architecture
The digital I/O control architecture for the PIO-D48/D48U/D48SU and PEX-D48 are demonstrated in
Figure 2.3. The operation method used for the control signal is presented below.

RESET\ is in the Low-state

all D/I/O operation is disabled

RESET\ is in the High-state

all D/I/O operation is enabled.

If D/I/O is configured as a D/I port

D/I= external input signal.

DI ports can be configured as either pull-high or pull-low by setting the JP2/3/4/5/6/7
jumpers (shorted 1-2=pull-high; shorted 2-3= pull-low).

If D/I/O is configured as a D/O port

D/I = read back D/O.

If D/I/O is configured as D/I port

sending data to a digital input port will only change the
D/O latch register. The latched data will be output when the port is configured as digital
output and is activated right away.
Figure 2-3