4 - 4
LINE
DESCRIPTION
VCC
The voltage from the attached battery pack.
CPU5
Common 5 V for the CPU (IC8) converted from the
VCC line at the CPU5 regulator circuit (IC12).
SW5V
Common 5 V line converted from the VCC line at the
SW5 regulator circuit (Q55–Q57, D39) controlled by
the "PWRON" signal.
T5
5 V for the transmit circuits regulated from the SW5V
line by the T5 regulator (Q22).
The regulator is controlled by the "T5C" signal from the
CPU (IC8, pin 80).
PS5
5 V for the power save line regulated from the SW5V
line by the PS5 regulator (Q54).
The regulator is controlled by the "PS5C" signal from
the CPU (IC8, pin 92).
R5
5 V for the receive circuits regulated from the SW5V
line by the R5 regulator (Q21).
The regulator is controlled by the "R5C" signal from
the CPU (IC8, pin 82).
VCO5
5 V for the VCO circuit regulated from the SW5V line
by the VCO5 regulator (Q11).
The regulator is controlled by the "PSVCO" signal from
the CPU (IC8, pin 62).
+5V
5 V for the optional unit power supply regulated from
the VCC line by the option power supply regulator
(Q61, Q62, D51).
The regulator is controlled by the "OP_PS" signal from
the CPU (IC8, pin 59).
4-5 POWER SUPPLY CIRCUITS
4-5-1 VOLTAGE LINES
4-6 PORT ALLOCATION
4-6-1 CPU (IC8)
PIN
NUMBER
PORT
NAME
DESCRIPTION
1
LVIN
Input port for PLL lock voltage.
3
REMO
Input port for remote control micro-
phone.
4
SD
Input por t for receiving signal
strength detect signal.
5
CTCIN
Input port for CTCSS/DTCS signals.
7
DET
Input port for weather alert tone detect
signal.
8
LEDC
Outputs LCD backlight control signal.
HIGH : Lights ON
9
PTT
Input port for [PTT].
10
MICS
Outputs AF filter switch (IC4) control
signal.
HIGH : While transmiting
11
AN
Output ports AN switch (IC14) con-
trol signal.
12
DIGITAL
Input port for UT-118 accept/refuse
signal.
LOW : Accept
13
UN_SEC
Output ports UN_SEC switch (IC14)
control signal.
15
CSHIFT
Outputs CPU (IC8) clock control signal.
19
RESET
Input port for "RESET" signal.
25
PWRSW
Input port for [PWR].
LOW : While pushing [PWR]
PIN
NUMBER
PORT
NAME
DESCRIPTION
26
NOIS
Input port for "NOIS" signal.
28
ESDA
I/O port for EEPROM (IC7).
29
ESCK
Outputs clock signal for EEPROM
(IC7).
30
CLIN
Input port for cloning data.
31
CLOUT
Output port for cloning data.
32
OPSO
Outputs serial data for optional unit.
33
SI
Input port for DTMF decode signal.
34
SECRET
Outputs secret switch (IC14) control
signal.
35
BUSY
Outputs receive detection (busy)
signal to UT-118.
40–42
OPT1–OPT3
I/O ports for optional unit.
43
ALC
Outputs ALC switch (IC13) control
signal.
HIGH : During digital mode operation.
44
THROUGH
Outputs ALC switch (IC13) control
signal.
HIGH : During analog mode operation.
45
DI_SEC
Outputs moddulation/demodulation
mode switching signal.
HIGH : During digital mode operation
46
MMUTE
Outputs analog switch (IC4) control
signal.
49
RMUTE
Outputs audio mute signal.
HIGH : While muting
52–54
OPV1–OPV3
Input ports for optional unit type
detect signal.
55
TX_DIGI
Outputs transmit audio frequency
characteristic control signal.
LOW : During digital mode operation.
56
PTTO
Input port for transmit request con-
trol signal from UT-118.
57
PTTI
Output port for transmit request con-
trol signal to UT-118.
58
D5VC
Output port for D5VC line (5 V power
supply; IC22) control signal.
HIGH : Power ON
59
OP_PS
Outputs option power supply (Q61,
Q62, D51) control signal.
HIGH : Power ON
60
OPSCK
Outputs clock signal for optional unit.
61
RX_MUTE
Input port for RX mute signal for
digital mode operation.
62
PSVCO
Outputs PS5 regulator (Q22) control
signal.
LOW : Power ON
63
PLPS
Outputs power save control signal to
the PLL IC (IC19).
LOW : Power saved
64
DASTB
Outputs strobe signal to D/A conver-
tor (IC10).
66
DADATA
Outputs serial data to D/A convertor
(IC10).
67
PLLSW
Outputs PLL loop filter switch (IC20)
control signal.
68
PLLCK
Outputs clock signal to PLL IC (IC19).
69
PLLDATA
Outputs serial data to the PLL IC (IC19).
Содержание IC-V82
Страница 1: ...6 42 3 6 2 iC v82 3 26 5...
Страница 34: ...3 COM NC...