3 - 7
3-5 PORT ALLOCATIONS
3-5-1 CPU (LOGIC UNIT; IC101)
Pin
number
1
9
11
12
14
15
16
17
18
19
21
22
23
24
25
26
36
37
38
39
40
41
42
43
44
45
46
47
48
Port
name
KEY6
CRES
PWRK
DUD
DAST
RSTB
ISTB
ASTB
ECS
MCK
MDAT
PCK
PST1
PDAT
PST2
PST3
SSBK
CWK
AMK
FMK
FILK
TSK
PREK
ATTK
NRK
ANFK
NBK
AGCK
VMK
Description
Input port for [0] and [ENT] switch
from the 10-key.
Input port for the reset signal.
Low :
While the reset switch is
pushed.
Input for the [POWER] switch.
Low :
While [POWER] switch is
pushed.
Input port for the UP signal from the
[MAIN DIAL].
Outputs strobe signals for the D/A
converter (LOGIC unit; IC351).
Outputs strobe signals for the shift
registor (MAIN unit; IC551, IC552).
Outputs strobe signals for the shift
registor (MAIN unit; IC1602).
Outputs strobe signals for the shift
registor (MAIN unit; IC1601).
Outputs ECS signals for the EEPROM
(LOGIC unit; IC231).
Outputs clock signal to the EEPROM
and shift registors.
Outputs data signals to the EEPROM,
shift registors, etc.
Outputs clock signals to the PLL IC
(PLL unit; IC21) and the DDS IC (PLL
unit; IC151, IC201).
Outputs strobe signals for the PLL IC.
Outputs data signals to the PLL IC and
the DDS IC.
Outputs strobe signals for the DDS IC
(IC151).
Outputs strobe signals for the DDS IC
(IC201).
Input port for the [SSB] switch.
Input port for the [CW] switch.
Input port for the [AM] switch.
Input port for the [FM] switch.
Input port for the [FIL] switch.
Input port for the [TS] switch.
Input port for the [P.AMP] switch.
Input port for the [ATT] switch.
Input port for the [NR] switch.
Input port for the [ANF] switch.
Input port for the [NB] switch.
Input port for the [AGC] switch.
Input port for the [V/M] switch.
Pin
number
49
50
51
52
53
54
55
56
57
63
77
78
79
80
81
82
83
84
90
91
92
93
94
Port
name
MWK
CLRK
SELK
SCAK
UPK
DNK
LOCK
SETK
CLKK
DRES
PWRS
BEEP
RXS
AGRS
SQLS
BKUP
DCK
RECS
AFGL
RFGL
PB1L
PB2L
FMNL
Description
Input port for the [MW] switch.
Input port for the [CLR] switch.
Input port for the [SEL] switch.
Input port for the [SCAN] switch.
Input port for the [UP] switch.
Input port for the [DN] switch.
Input port for the [LOCK] switch.
Input port for the [SET] switch.
Input port for the [CLOCK] switch.
Outputs reset signal to the PLL IC and
DDS IC.
Low: PLL IC and DDS IC is reset.
Outputs control signal for the regulator
circuit (MAIN unit; IC1371 and
D1371).
Outputs beep audio signals.
Outputs control signal for the R8 regu-
lator circuit (MAIN unit; Q1381,
Q1382, D1381).
• Outputs AGC reset signal to the
AGC delay control circuit (MAIN unit;
Q1066).
• Outputs control signal for the AGC
delay control circuit (MAIN unit;
Q1061, Q1064–Q1066).
Outputs squelch control signal to the
AF selector circuit (MAIN unit;
IC1201).
Input port for the BKUP signal from
the reset circuit (LOGIC unit; IC391).
Input port for the UP signal from the
[MAIN DIAL].
Outputs control signal for the remote
recording driver.
Input port for the AF gain signal from
the [AF] volume on the front panel.
Input port for the SQL/RF gain signal
from the [SQL/RF] volume on the front
panel.
Input port for the PBT1 signal from the
[TWIN PBT] volume on the front
panel.
Input port for the PBT2 signal from the
[TWIN PBT] volume on the front
panel.
Input port for the FM noise squelch
signal from the FM detector circuit
(MAIN unit; IC1001 and X1001).