3 - 3
3-3 PLL CIRCUITS
3-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by a
crystal oscillator and the divided ratio of the programmable
divider. IC3 is a dual PLL IC which controls both VCO cir-
cuits for Tx and Rx.
The PLL circuit , using a one chip PLL IC (IC3), directly gen-
erates the transmit frequency and receive 1st IF frequency
with VCOs. The PLL sets the divided ratio based on serial
data from the CPU on the LOGIC unit and compares the
phases of VCO signals with the reference oscillator fre-
quency. The PLL IC detects the out-of-step phase and out-
put from pins 8 and 13 for Tx and Rx, respectively. The ref-
erence frequency (15.2 MHz) is oscillated at X1.
3-3-2 TX LOOP
The generated signal at the TX-VCO (Q4, D6, D7) enters
the PLL IC (IC3, pin 2) and is divided at the programmable
divider section and is then applied to the phase detector
section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 8.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R41–R43, C75–C77), and then
applied to varactor diodes (D6, D7) of the TX-VCO to stabi-
lize the oscillated frequency.
3-3-3 RX LOOP
The generated signal at the RX-VCO (Q5, D8) enters the
PLL IC (IC3, pin 19) and is divided at the programmable
divider section and is then applied to the phase detector
section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 13.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R34, R37, R38, C64, C73), and
then applied to varactor diode (D8) of the RX-VCO to stabi-
lize the oscillated frequency. The lockvoltage is also used for
the receiver circuit for the bandpass filter center frequency.
The lock voltage from the loop filter is amplified at the buffer-
amplifier (Q6) and then applied to the RF circuit.
3-3-4 VCO CIRCUIT
The VCO outputs from Q4 (Tx) and Q5 (Rx) are buffer-
amplified at Q7 and Q9, and are then sent to the T/R switch
(D9). The receive LO signal is applied to the 1st mixer circuit
(Q2) through a low-pass filter, and the transmit signal is
applied to the pre-drive amplifier (Q10). A portion of the VCO
output is reapplied to the PLL IC (IC10, pin 2 or pin 13) via
Q8.
3-4 POWER SUPPLY CIRCUITS
Shift register
×
2
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.2 MHz
30.4 MHz signal
to the FM IF IC
Q4, D6, D7
TX VCO
RX VCO
Buffer
Buffer
Buffer
Q9
Q8
Q7
3
4
5
P.STB
IC3 (PLL IC)
CK
DATA
to transmitter circuit
to 1st mixer circuit
D9
17
16
8
2
Q5, D8
LINE
HV
HVS
5V
R5
T5
DESCRIPTION
The voltage from the connected DC power sup-
ply.
Same voltage as the HV line which is passed
through the [PWR] switch (VR-A unit; R1).
Common 5 V converted from the HVS line at the
5V regulator circuit (IC8).
Receive 5 V converted from the 5V line at the R5
regulator circuit (Q19, Q20). The regulated volt-
age is applied to the receiver circuits.
Transmit 5 V converted from the 5V line at the T5
regulator circuit (Q17, Q18).
• PLL CIRCUIT