Icom IC-M402, Руководство по обслуживанию

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4 - 3
4-2-5 APC CIRCUIT (MAIN UNIT)
The APC circuit stabilizes transmit output power.
The RF output signal from the power amplifier (IC3) is
detected at the power detector circuit (D8, D9, L12) and is
then applied to one of the differential amplifier inputs (Q15,
pin 5) via the High/Low control circuit (R71, Q16). The
applied voltage controls the differential amplifier output
(Q15, pin 2) and the bias voltage control (Q12). Thus the
APC circuit maintains a constant output power.
4-3 PLL CIRCUITS
4-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by a
crystal oscillator and the divided ratio of the programmable
divider.
IC2 on the MAIN unit is a dual PLL IC which controls both
VCO circuits for Tx and Rx, and contains a prescaler, pro-
grammable counter, programmable divider, phase detector,
charge pump, etc.
The PLL circuit , using a one chip PLL IC (MAIN unit; IC2),
directly generates the transmit frequency and receive 1st IF
frequency with VCOs. The PLL sets the divided ratio based
on serial data from the CPU on the LOGIC unit and com-
pares the phases of VCO signals with the reference oscilla-
tor frequency. The PLL IC detects the out-of-step phase and
output from pins 8 for Tx and Rx. The reference frequency
(21.25 MHz) is oscillated at X2 (MAIN unit).
4-3-2 TX AND RX LOOP (MAIN UNIT)
The generated signal at the VCO (Q4, Q5, Q6, D1–D4)
enters the PLL IC (IC2, pin 2) and is divided at the pro-
grammable divider section and is then applied to the phase
detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 8.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R29–R31, R41, C41, C42, C50,
C51), and is then applied to varactor diodes (D3, D4) of the
VCO to stabilize the oscillated frequency. The lock voltage
from the loop filter is amplified at the buffer amplifier (Q7)
and then applied to the RF circuit.
T5
D8
D9
L12
"TMUT" signal from the CPU
(LOGIC board; IC1, pin 83)
HV
1
2 3
4
HI/LO
"TXDET" signal to the CPU
(LOGIC board; IC1, pin 92)
Q12
Q15
Q14
Q16
C93
R69
R70
Q11
YGR
amp.
RF signal
from PLL
to antenna
RF detector
circuit
APC control circuit
Power module
IC3
R74
R73
R71
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X2
21.25 MHz
21.25 MHz signal to the
FM IF IC (IC1, pin 2)
VCO
Buffer
Buffer
Buffer
Q9
Q8
Q7
3
4
5
PSTB
IC2 (PLL IC)
PCK
PDATA
to transmitter circuit
to 1st mixer circuit
D6
D5
17
16
8
2
Q4 Q6, D1 D4
• APC CIRCUIT
• PLL CIRCUIT