5 - 4
(MAIN unit; IC16; pin 3), and the “T2” signal from the D/A
converter (MAIN unit; IC12, pin 23), controlled by the CPU
(MAIN unit; IC22), is applied to the other input for reference.
When antenna impedance is mismatched, the detected
voltage exceeds the power setting voltage. Then the output
voltage of the differential amplifi er (MAIN unit; IC16, pin 4)
controls the input current of the drive (PA unit; Q702) and
power (PA unit; Q701) amplifi ers to reduce the output power.
5-3 PLL CIRCUITS
5-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX and RX VCO circuits (Q16,
Q17, D9–D13). The oscillated signal is amplifi ed at the buffer
amplifi ers (Q14, Q15) and then applied to the PLL IC (IC21,
pin 6) after being passed through the low-pass filter (L32,
C206, C208).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The applied
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided
signal is detected on phase at the phase detector using the
reference frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
5-3-2 VCO CIRCUITS (MAIN UNIT)
The VCO circuits contains a separate RX VCO (Q17, D9,
D11) and TX VCO (Q16, D10, D12, D13). The oscillated
signal is amplifi ed at the buffer amplifi ers (Q15, Q29) and is
then applied to the T/R switch (D16, D17). Then the receive
1st LO (Rx) signal is applied to the 1st mixer (Q6) and the
transmit (Tx) signal to the YGR amplifier circuit (PA unit;
Q704).
A portion of the signal from the buffer amplifi er (Q15) is fed
back to the PLL IC (IC21, pin 6) via the buffer amplifi er (Q14)
as the comparison signal.
Shift register
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X2
15.3 MHz
10
Buffer
Q15
Buffer
Q21
Buffer
Q29
Buffer
Q14
14
15
16
SCK
SO
PLST
to transmitter circuit
to 1st mixer circuit
D16
D17
4
6
Q16, D10, D12, D13
TX VCO
Q17, D9, D11
RX VCO
IC21 LMX2352
3
45.9 MHz 2nd LO
signal to the FM IF IC
(IC9, pin 2)
Tripler
Q22
"LVIN" signal to the CPU
(IC22, pin 49)
LPF
LINE
VCC
+5V
S5V
R5V
T5V
DESCRIPTION
The voltage from the connected battery pack.
Common 5 V converted from the VCC line at the
+5 regulator circuit (IC17). The output voltage is
supplied to buffer amplifiers (Q21), PLL IC
(IC21), etc.
Common 5 V converted from the VCC line at the
S5 regulator circuit (Q26–Q28). The output volt-
age is supplied to the ripple filter (Q20), etc.
Receive 5 V converted from the S5V line at the
R5 regulator circuit (Q25). The output voltage is
supplied to the tripler (Q22), FM IF IC (IC9), IF
amplifier (Q7), 1st mixer (Q6), RF amplifier (Q5),
etc.
Transmit 5 V converted from the S5V line at the
T5 regulator circuit (Q24). The output voltage is
supplied to the APC amplifier (IC16), PA unit, etc.
• PLL CIRCUIT
5-4 POWER SUPPLY CIRCUITS
