4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the RX VCO (Q11, D6, D7) and
TX VCO (Q12, D8, D9). The oscillated signal is amplified
at the buffer amplifier (Q20). The output signal frequency is
doubled at Q19, and is then applied to the PLL IC (IC4, pin 6)
after being passed through the bandpass filter (Q5, D3, D5,
L4, L47, L48, C85, C104, C105, C123, C519–521).
Q5, D3 and D5 switch the filtering frequencies between TX
and RX which is controlled by TXC.
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The applied
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the MAIN CPU. The divided
signal is detected on phase at the phase detector using the
reference frequency and output from pin 8. The output sig-
nal is passed through the loop filter (Q46, Q47) and is then
applied to the VCO circuit.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUITS (MAIN UNIT)
The VCO circuits contains a separate RX VCO (Q11, D6,
D7) and TX VCO (Q12, D8, D9). The oscillated signal is
amplified at the buffer amplifiers (Q20, Q22) and is then
applied to the T/R switch (D19, D20). Then the receive 1st
LO (Rx) signal is applied to the 1st mixer (L22, L23, D16)
and the transmit (Tx) signal to the YGR amplifier circuit (Q23).
A portion of the signal from the buffer amplifier (Q20) is fed
back to the PLL IC (IC4, pin 6) via the doubler circuit (Q19)
as the comparison signal.
4 - 4
4-4 POWER SUPPLY CIRCUITS
Line
Description
HV
The voltage from a DC power supply.
VCC
The same voltage as the HV line which is
controlled by the power switch circuit (Q41,
Q42). When the [ ] is pushed, the MAIN
CPU outputs the "PWR" control signal to the
power switch circuit to turn the circuit ON.
CPU 5
Common 5 V converted from the HV line
at the CPU5V regulator circuit (IC40). The
output voltage is applied to the MAIN CPU
(IC23) and EEPROM (IC26), etc.
5V
Common 5 V converted from the CPU5V
line at the 5 V regulator circuit (Q31, Q32).
The output voltage is applied to the PLL IC
(IC4) and D/A converter IC (IC30), etc.
8V
Common 8 V converted from the VCC line
at the 8 V regulator circuit (IC36). The output
voltage is applied to the buffer amplifi er (Q22)
and 1st LO amplifi er (Q21), etc.
T8V
Transmit 8 V controlled by the T8V regulator
circuit (Q34) using the "TMUT" signal from
the MAIN CPU (IC23). The output voltage is
applied to the driver (Q23) and PA amplifi ers
(IC29), etc.
R8V
Receive 8 V controlled by the R8V regulator
circuit (Q30) using the "TXC" signal from
the MAIN CPU (IC23). The output voltage is
applied to the RF amplifi er (Q24) and 1st IF
amplifi er (Q6), etc.
Shift register
×
3
×
2
Prescaler
Phase
detector
Loop
filter
Programable
counter
Programable
divider
X2
15.3 MHz
45.9 MHz signal
to the FM IF IC
16
Q11, D6, D7
RX VCO
TX VCO
Buffer
Buffer
Q22
Q19
Q20
Q1
Q46, Q47
19
18
17
PLST
IC4 (PLL IC)
SO
SCK
to transmitter circuit
to 1st mixer circuit
D20
D19
8
5
Q12, D8, D9
BPF
• PLL CIRCUIT
