4 - 6
4-3 PLL CIRCUITS
4-3-1 GENERAL DESCRIPTION
The PLL unit contains 2 DDS circuits for generating a 1st LO
signal (64.485–94.455 MHz variable) and a BFO frequency
(453.5–456.5 kHz). The 1st LO PLL employs a 1 loop DDS
PLL whose reference oscillator is also used as the 2nd LO
signal (64.00 MHz fixed). The DDS (Direct Digital
Synthesizer) circuit performs signal-sampling, generation of
digital sine wave and digital phase detection.
4-3-2 1ST LO CIRCUIT (PLL UNIT)
The PLL contain one VCO circuit (Q18, D4) for all HF band
coverage within 1 Hz step. The VCO oscillation signal is
buffer-amplified at Q26 and is then amplified at Q29, Q32
and Q30. The resulting signal is applied to the DDS IC (IC6).
The DDS IC outputs pulse-type signals. The signals are
applied to the loop filter to be converted into DC voltage
(lock voltage).
The lock voltage is applied to the varactor diode (D4) in the
VCO circuit to change the capacitance of this diode and con-
trol the oscillation frequency.
The VCO oscillating signal is then buffer-amplified at the
buffer amplifier (Q26), and amplified at the LO amplifier
(Q28), and finally applied to the MAIN unit as a 1st LO sig-
nal.
4-3-3 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
The reference oscillator circuit consists of Q9 and X1. A
32.00 MHz reference frequency is oscillated to produce a
2nd LO signal, DDS reference frequency and BFO DDS
clock signal.
The 32.00 MHz reference frequency is doubled at Q10 to
obtain the 2nd LO signal. The resulting 64.00 MHz signal is
filtered at the bandpass filter and is then applied to the MAIN
unit via J1 as the 2nd LO signal.
4-4 LOGIC CIRCUITS
4-4-1 BAND SELECTION DATA (MAIN UNIT)
To select the correct bandpass filter and low-pass filter, the
CPU outputs the following band selection data from the I/O
expander (MAIN unit; IC3001) depending on the displayed
frequency.
The band voltage is produced at the D/A converter (IC3301)
and IC2101c.
4-4-2 RIT CONTROL (FRONT UNIT)
The [RIT] control shifts the “RITL” voltage in order to shift the
receive frequency. The voltage is applied to the A/D con-
verter section of the CPU (IC1, pin 92). The CPU shifts the
N-data for the DDS IC.
• FREQUENCY CONSTRUCTION
64.485–
97.455 MHz
453.3–
456.5 kHz
64.0 MHz
ANT
1st mixer
Q1101–Q1104
IC2
Q10
BFO
2nd LO
1st LO
PLL unit
MAIN unit
DDS
DDS
Crystal
filter
2nd mixer
D401
Demodulator
64.455 MHz
BPF
455 kHz
to AF circuit
Reference
oscillator
X1: 32.0 MHz
Q9
IC6
Q18
LPF
✕
2
BPF
Loop
filter
BPF
• Band selection data
Band
0.03–1.59999 MHz
1.6–1.99999 MHz
2.0–3.99999 MHz
4.0–7.99999 MHz
8.0–10.99999 MHz
11.0–14.99999 MHz
15.0–21.99999 MHz
22.0–30.00000 MHz
Band
voltage
7.4 V
6.0 V
5.0 V
0 V
4.0 V
3.1 V
2.2 V
BPF
B0
B1
B2
B3
B4
B5
B6
B7
LPF
L1
L2
L3
L4
L5
L6
