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4-1-10 SSB/CW DEMODULATOR CIRCUITS

(MAIN UNIT)

In SSB or CW mode, the 2nd IF signal from the IF amplifier
(Q1601) is mixed with the BFO signal from the PLL unit at
the product detector (IC2001) to demodulate the 2nd IF sig-
nal into AF signals. The detected signals (AF) from IC2001
(pin 1) are applied to the AF input mode selector switch
(IC2102, pin 7).

4-1-11 AM DEMODULATOR CIRCUITS

(MAIN UNIT)

In AM mode, the 2nd IF signal from the buffer amplifier
(Q1601) passes through C1905 and is detected at D1901.
The detected signal (AF) is then applied to the AF input
mode selector switch (IC2102, pin 6).

4-1-12 AF INPUT MODE SELECTOR SWITCH

(MAIN UNIT)

The AF signal from one of the detector circuits is applied to
the AF input mode selector switch (IC2102). IC2102 consists
of analog switches which are selected with a mode signal
and the squelch control signal. The AF signal is output from
IC2102 (pin 1) and then applied to the AF amplifier circuit.

4-1-13 AGC CIRCUIT (MAIN UNIT)

The AGC (Automatic Gain Control) circuit reduces IF ampli-
fier gain to keep the audio output at a constant level.

The voltage on the AGC line (Q1805, collector) determines
the receiver gain. The voltage is usually set by D1803 and
the resistance ratio of R1812 and R1813.

The 2nd IF signal from the buffer amplifier (Q1601) is detect-
ed at the AGC detector (D1803) and is then applied to the
DC amplifier (Q1805). –5 V is applied to the Q1805 emitter
to activate the AGC line with minus voltage.

When receiving strong signals, the detected voltage
increases and the voltage of the AGC line decreases via the
DC amplifier (Q1805). As the AGC line is used for the bias
voltage of the IF amplifiers (Q1301, Q1201, Q1603), IF
amplifier gain is decreased.

When the strong signal disappears, C1804 and R1809
release the AGC line voltage in CW or RTTY mode to obtain
a fast AGC release time. While in SSB or AM mode, C1803,
C1805, R1808 and C1802, R1807 are connected in parallel
to obtain a appropriate AGC characteristics (middle or slow
AGC release time), respectively.

4-1-14 S-METER CIRCUIT (MAIN UNIT)

The S-meter circuit indicates the relative received signal
strength while receiving by utilizing the AGC voltage which
changes depending on the received signal strength.

The AGC bias voltage (time constant line) is applied to a dif-
ferential amplifier (IC1701d, pin 13) where the difference
between the bias and reference voltage is detected.

The S-meter signal is applied to the A/D converter section in
the CPU (LOGIC unit; IC1, pin 98) and the S/RF indicator
displays the relative signal strength.

4-1-15 SQUELCH CIRCUIT (MAIN UNIT)

The squelch circuit mutes audio output when the S-meter
signal is lower than the [SQL] control setting level.

The S-meter signal from IC1701d (pin 14) is applied to the
CPU (LOGIC unit; IC1) to be compared with the threshold
level set by the [SQL] control.

When the S-meter signal is lower than the threshold level,
the CPU outputs control signal to the AF input mode selec-
tor switch (IC2102, pin 5) via the D/A converter (IC3006).
This cuts the AF signal OFF. The CPU also controls turning
OFF the [RX] indicator, and CPU (pin 43) outputs “SQLS”
signal to the [MIC] connector (pin 6) and [ACC] connector
(pin 13).

4-1-16 AF AMPLIFIER CIRCUIT (MAIN UNIT)

The AF amplifier amplifies the AF input signal to a suitable
driving level for the speaker.

The AF signal from the AF input mode selector switch is
applied to the AF pre-amplifier (IC2101a). The CW side tone
signal is also applied to IC2101a.

• AGC CIRCUIT

AGC line

RFGV
(RF/SQL control)

AGC

SLOW

RESET

Q1805

8 V

–5 V

D1803

C1815

2nd IF
signal