IBM Power System POWER7 Series, Руководство по оптимизации и настройке

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Chapter 2. The POWER7 processor
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Page size and shared memory
To back shared memory segments of an application with large pages, specify the SHM_LGPAGE
and SHM_PIN flags in the shmget() function. If large pages are unavailable, the 4 KB pages
back the shared memory segment.
Support for specifying the page size to use for the shared memory of a process with the
SHMPSIZE environment variable is available starting in IBM AIX 5L Version 5.3 with the
5300-08 Technology Level, or later, and AIX Version 6.1 with the 6100-01 Technology Level,
or later.
Monitoring page size that is used by an application
Monitoring page size is accomplished by running the following commands:
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򐂰 The ps command can be used to monitor the base page sizes that are used for process
data, stack, and text.
򐂰
The
vmstat
command has two options available to display memory statistics for a specific
page size.
򐂰 The vmstat -p command displays global vmstat information, along with a breakdown of
statistics per page size.
򐂰 The vmstat -P command displays per page size statistics.
For more information about this topic, see 2.4, “Related publications” on page 51.
2.3.2 Cache sharing
Power Systems consist of multiple processor cores and multiple processor chips that share
caches and memory in the system. The architecture uses a processor and memory layout
that you can use to scale the hardware to many nodes of processor chips and memory. One
advantage is that systems can be used for multiple workloads and workloads that are large.
However, these characteristics must be carefully weighed in the design, implementation, and
evaluation of a workload. Aspects of a program, such as the allocation of data across cores
and chips and the layout of data within a data structure, play a key role in maximizing
performance, especially when scaling across many processor cores and chips.
Power Systems use a cache-coherent SMP design in which all the memory in the system is
accessible to all of the processor cores in the system, and all of the cache is
coherently maintained:
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1. Any processor core on any chip can access the memory of the entire system.
2. Any processor core can access the contents of any core cache, even if it on a
different chip.
In POWER7 Systems, each chip consists of eight processor cores, each with on-core L1
instruction and d-caches, an L2 cache, and an L3 cache, as shown in Figure 2-2 on page 31.
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Multiple page size support, available at:
http://pic.dhe.ibm.com/infocenter/aix/v7r1/topic/com.ibm.aix.prftungd/doc/prftungd/multiple_page_siz
e_support.htm
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Of NUMA on POWER7 in IBM i, available at:
http://www.ibm.com/systems/resources/pwrsysperf_P7NUMA.pdf
Processor core access: In both of these cases, the processor core can access only
memory or cache that it has authorized access to using normal operating system and
Hypervisor memory access permissions and controls.