Chapter 2. System-Board Features
The following figure shows some possible configurations for the supported DIMMs.
Note: Values in the following table are represented in megabytes (MB).
Figure 1. Memory Configurations
Total Memory (MB)
Mem 0
Mem 1
Mem2
2
16
16
0
0
32
16
16
0
32
32
0
0
48
16
16
16
48
32
16
0
64
32
16
16
64
32
32
0
64
64
0
0
96
32
32
32
96
64
32
0
128
64
32
32
128
64
64
0
128
128
0
0
160
32
64
64
192
64
64
64
224
32
64
128
256
128
64
64
256
128
128
0
288
32
128
128
384
128
128
128
PCI Bus
The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI bus are:
Integrated arbiter with multitransaction PCI arbitration acceleration hooks
Zero-wait-state, microprocessor-to-PCI write interface for high performance graphics
Built-in PCI bus arbiter with support for up to five masters
Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
PCI-to-DRAM posting 18 Dwords
PCI-to-DRAM up to 100+ MB/sec bandwidth
Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle
PCI 2.1 compliant
Delayed transaction
PCI parity checking and generation support
2
Only in some Pentium II models
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Technical Information Manual
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