IBM PC 300GL Type 6272, Техническое руководство

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Chapter 2. System Board Features
PCI Bus
The fully synchronous 30/33 MHz PCI bus originates in the chipset. Features of the PCI bus are:
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Zero wait state microprocessor-to-PCI write interface for high performance graphics
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Built-in PCI bus arbiter with support for up to five masters
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Microprocessor-to-PCI memory write posting with 5 Dword deep buffers
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Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
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PCI-to-DRAM posting 18 Dwords
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PCI-to-DRAM up to 120 MB/sec bandwidth
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Multi-transaction timer to support multiple short PCI transactions within one PCI ARB cycle
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PCI 2.1 compliant
Bus Master IDE Interface
The system board incorporates a PCI-to-IDE interface that complies with the AT Attachment Interface with
Extensions. The subsystem that controls direct access storage devices (DASD) is integrated with the IDE
interface.
The chipset functions as a bus master for the IDE interface. The chipset is PCI 2.1 compliant; it connects
directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and IDE bus. The
chipset is capable of supporting PIO mode 0-4 devices and IDE DMA mode 0-2 devices.
A ribbon cable provided with the computer can attach up to four IDE devices to the IDE connectors on the
system board. The IDE devices receive their power through a four-position power cable cont5,
+12, and ground voltage. When adding devices to the IDE interface, one device is designated as the
primary or master device and another is designated as the secondary or subordinate device. These
designations are determined by switches or jumpers on each device.
For the IDE interface, no resource assignments are given in the system memory or the direct memory
access (DMA) channels. For information on the resource assignments, see “Input/Output Address Map”
on page 45 and Figure 52 on page 50 (for IRQ assignments).
Two connectors are provided on the system board for the IDE interface. For information on the connector
pin assignments, see “IDE Connectors” on page 34.
PCI to ISA Bridge
On the system board, the chipset provides the interface between the peripheral component interface (PCI)
and industry standard architecture (ISA) buses. The chipset is used to convert PCI bus cycles to ISA bus
cycles; the chipset also includes all the subsystems of the ISA bus, including two cascaded interrupt
controllers, two DMA controllers with four 8-bit and three 16-bit channels, three counters equivalent to a
programmable interval timer, and power management. The ISA bus operates at speeds of 7.5 MHz with a
60 MHz microprocessor bus and 8.25 MHz with a 66 MHz microprocessor bus (one-quarter of the PCI bus
speed).
For the ISA bus, no resource assignments are given in the system memory or the DMA channels. For
information on resource assignments, see “Input/Output Address Map” on page 45 and Figure 52 on
page 50 (for IRQ assignments).
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Technical Information Manual