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Chapter 6. System Compatibility

Chapter 6. System Compatibility

This chapter discusses some of the hardware, software, and BIOS compatibility issues for the computer.
Refer to

Compatibility Report for a list of compatible hardware and software options.

Hardware Compatibility

This section discusses hardware, software, and BIOS compatibility issues that must be considered when
designing application programs.

Many of the interfaces are the same as those used by the IBM Personal Computer AT. In most cases,
the command and status organization of these interfaces is maintained.

The functional interfaces are compatible with the following interfaces:

Intel 8259 interrupt controllers (edge-triggered mode)

National Semiconductor NS16450 and NS16550A serial communication controllers

Motorola MC146818 Time of Day Clock command and status (CMOS reorganized)

Intel 8254 timer, driven from a 1.193 MHz clock (channels 0, 1, and 2)

Intel 8237 DMA controller, except for the Command and Request registers and the Rotate and Mask
functions; the Mode register is partially supported

Intel 8272 or 82077 diskette drive controllers

Intel 8042 keyboard controller at addresses hex 0060 and hex 0064

All video standards using VGA, EGA, CGA, MDA, and Hercules modes

Parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode

Use the above information to develop application programs. Whenever possible, use the BIOS as an
interface to hardware to provide maximum compatibility and portability of applications among systems.

Hardware Interrupts

Hardware interrupts are level-sensitive for PCI interrupts and edge-sensitive for ISA interrupts. The
interrupt controller clears its in-service register bit when the interrupt routine sends an End-of-Interrupt
(EOI) command to the controller. The EOI command is sent regardless of whether the incoming interrupt
request to the controller is active or inactive.

The interrupt-in-progress latch is readable at an I/O-address bit position. This latch is read during the
interrupt service routine and might be reset by the read operation or it might require an explicit reset.

Note: For performance and latency considerations, designers might want to limit the number of devices

sharing an interrupt level.

With level-sensitive interrupts, the interrupt controller requires that the interrupt request be inactive at the
time the EOI command is sent; otherwise, a new interrupt request will be detected. To avoid this, a
level-sensitive interrupt handler must clear the interrupt condition (usually by a read or write operation to
an I/O port on the device causing the interrupt). After processing the interrupt, the interrupt handler:

1. Clears the interrupt

2. Waits one I/O delay

24

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Copyright IBM Corp. November 1998

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Содержание PC 300GL Type 6267

Страница 1: ...Technical Information Manual PC 300GL Types 6267 6277 and 6287 ...

Страница 2: ...iodically made to the information herein these changes will be incorporated in new editions of the publication IBM may make improvements and or changes in the product s and or the program s described in this publication at any time This publication was developed for products and services offered in the United States of America IBM may not offer the products services or features discussed in this d...

Страница 3: ...ubsystem 8 Integrated AGP S3 Trio3D SVGA Super Video Graphics Array 8 Video Memory 9 Audio Subsystem 9 Input Output Controller 10 Diskette Drive Interface 10 Serial Ports 10 Parallel Port 11 Keyboard and Mouse Ports 11 Network Connection 11 Real Time Clock and CMOS 12 Flash EEPROM 12 Expansion Adapters 12 Physical Layout 13 System Board Types 6267 6277 and 6287 13 System Board Switches 13 Jumper 1...

Страница 4: ...itive Programs 27 Appendix A Connector Pin Assignments 28 AGP Monitor Port Connector 28 Memory Connectors 28 ISA Connectors 32 PCI Connectors 34 IDE Connectors 35 Diskette Drive Connector 36 Power Supply Connector 37 Modem Ring Wakeup and Wake on LAN Connectors 37 USB Port Connectors 37 Mouse and Keyboard Port Connectors 38 Serial Port Connector 38 Parallel Port Connector 39 Joystick MIDI Connecto...

Страница 5: ...Index 48 Contents v ...

Страница 6: ...eading Writing and Formatting Capabilities 25 24 AGP Monitor Port Connector Pin Assignments 28 25 System Memory Connector Pin Assignments 28 26 System Memory Connector Pin Input Output 30 27 ISA Connector Pin Assignments 32 28 PCI Bus Connector 34 29 PCI Connector Pin Assignments 34 30 IDE Connector Pin Assignments 36 31 Diskette Drive Connector Pin Assignments 36 32 Power Supply Connector Pin Ass...

Страница 7: ...tware contains information about the preinstalled software package Hardware Maintenance Manual This publication contains information for trained service technicians It is available at http www pc ibm com us cdt hmm html on the World Wide Web and it can also be ordered from IBM To purchase a copy refer to the Getting Help Service and Information section in PC 300GL User Guide Compatibility Report T...

Страница 8: ...es 2 10 1 MB equals 1048576 bytes 2 20 and 1 GB equals 1073741824 bytes 2 30 When expressing storage capacity MB equals 1000 KB 1024000 The value is determined by counting the number of sectors and assuming that every two sectors equals 1 KB Note Depending on the operating system and other system requirements the storage capacity available to the user might vary viii Technical Information Manual ...

Страница 9: ...security Security settings provided by the Configuration Setup Utility Program Power on and administrator password protection Startup sequence control Hard disk drive and diskette drive access control I O port control Cover lock loop U bolt and security cabling optional Operating system security Diskette write protection Integrated AGP S3 Trio3D SVGA video controller with 2 MB of SDRAM video memor...

Страница 10: ...ecific LAN frame is passed to the PC over the LAN To use the Wake on LAN feature the computer must be equipped with a network subsystem that supports Wake on LAN The menu used for setting the Wake on LAN feature is found in the Configuration Setup Utility Program Wake Up on Ring All models are configurable to turn on the computer after a ring is detected from an external or internal modem The menu...

Страница 11: ...Chapter 1 System Overview CMOS Save Restore utility program CMOS setup over LAN Wake Up on Ring Chapter 1 System Overview 3 ...

Страница 12: ...z FSB 512 KB L2 cache with ECC 32 bit microprocessor address bus Math coprocessor MMX technology which boosts the processing of graphic video and audio data L2 cache integrated into the microprocessor Cache operates at 1 2 processor core speed 4 way set associative Nonblocking More information on these microprocessors is available at http www intel com on the World Wide Web Celeron Microprocessor ...

Страница 13: ...interface is controlled by the 440BX chip set Synchronous dynamic random access memory SDRAM is standard The maximum amount of system memory is 384 MB on some models and 256 MB on some models For memory expansion some system board models provide three dual inline memory module DIMM connectors Other models provide two DIMM connectors 100 MHz DIMMs in sizes of 16 MB 32 MB 64 MB and 128 MB are suppor...

Страница 14: ...originates in the chip set Features of the PCI bus are Integrated arbiter with multitransaction PCI arbitration acceleration hooks Zero wait state microprocessor to PCI write interface for high performance graphics Built in PCI bus arbiter with support for up to five masters Microprocessor to PCI memory write posting with 5 Dword deep buffers Converts back to back sequential microprocessor to PCI ...

Страница 15: ...e system board the Intel PIIX4E bridge provides the interface between the peripheral component interface PCI and industry standard architecture ISA buses The chip set is used to convert PCI bus cycles to ISA bus cycles the chip set also includes all the subsystems of the ISA bus including two cascaded interrupt controllers two DMA controllers with four 8 bit and three 16 bit channels three counter...

Страница 16: ... support Advanced Power Management support Color space conversion Hardware scaling The PC 300GL has an AGP bus and is AGP 1 0 compliant The S3 Trio3D video subsystem supports the VESA Display Data Channel DDC standard 1 1 and uses DDC1 and DDC2B to determine optimal values during automatic monitor detection The video subsystem has the following resource assignments Figure 2 Video Subsystem Resourc...

Страница 17: ...page 28 Video Memory The video memory interface is controlled by an S3 Trio3D graphics controller Some models are shipped with 4 MB SGRAM with the video subsystem other models are shipped with 2MB SGRAM The video memory is 2 MB 256K X32 socket with 100MHz SGRAM The video memory can be upgraded from 2 MB SGRAM to 4 MB SGRAM with a 2 MB SGRAM 100 MHz SODIMM The SODIMM can be plugged into the SODIMM ...

Страница 18: ...following features Diskette drive interface Serial port Parallel port Keyboard and mouse ports General purpose I O ports Diskette Drive Interface The PC 300GL has four drive bays for installing internal devices The following is a list of devices that the diskette drive subsystem supports 1 44 MB 3 5 inch diskette drive 1 44 MB 3 5 inch 3 mode drive for Japan no BIOS support for 3 mode drive 1 2 MB...

Страница 19: ...resses and a fixed IRQ line and can operate without the mouse The mouse cannot operate without the keyboard because although it has a fixed IRQ line the mouse relies on the addresses of the keyboard for operation For the keyboard and mouse interfaces no resource assignments are given in the system memory addresses or DMA channels For information on the resource assignments see Input Output Address...

Страница 20: ...em board uses a 2 MB flash electrically erasable programmable read only memory EEPROM to store the basic input output system BIOS video BIOS IBM logo Configuration Setup Utility and Plug and Play data If necessary the EEPROM can be easily updated using a stand alone utility program that is available on a 3 5 inch diskette Expansion Adapters Each ISA expansion connector is a 16 bit slot and each PC...

Страница 21: ...ntained in a six position switch block on the system board are rocker switches The side of the rocker that is pushed down is the active side Switches 1 through 4 determine the speed of the microprocessor CPU and local processor bus Switch settings for the Intel microprocessors supported by PC 300GL are shown in the following table Note that the two speeds shown for each microprocessor are the micr...

Страница 22: ...age 2 of 2 Microprocessor Speed 66 MHz FSB Switches 1 4 Microprocessor Switch 1 Switch 2 Switch 3 Switch 4 Multiplier 266 MHz On On Off On 4 0 300 MHz Off On Off On 4 5 333 MHz On Off Off On 5 0 366 MHz Off Off Off On 5 0 Figure 8 Microprocessor Speed 100 MHz FSB Switches 1 4 Microprocessor Switch 1 Switch 2 Switch 3 Switch 4 Multiplier 300 MHz On Off On On 3 0 350 MHz Off Off On On 3 5 400 MHz On...

Страница 23: ...crophone connectors and joystick MIDI connector Connector Panel Connectors for features that are integrated into the system board can be identified by a symbol directly below the connector Connectors provided by an adapter might not have an identifying symbol For pinout details on connectors see Appendix A Connector Pin Assignments on page 28 1 2 Chapter 2 System Board Features 15 ...

Страница 24: ...mum 200 V AC Maximum 240 V AC Voltage switch setting 230 or 230 V Current rating 2 0 amps Input kilovolt amperes kVA approximately Maximum configuration 0 10 kVA Note Power consumption and heat output vary depending on the number and type of optional features installed and the power management optional features in use Heat Output Approximate heat output in British thermal units Btu per hour Minimu...

Страница 25: ...s to a 3 pin header on the system board Some Wake on LAN adapters have two headers a 3 pin right angle header for providing AUX5 Auxiliary 5 volts and a 2 pin straight header for connecting the wakeup signal to the system board These Wake on LAN adapter options will provide a Y cable that has the 3 pin system board connector on one end and splits into the 3 pin and 2 pin connectors required to int...

Страница 26: ...onnects to the system board with a 2 x 10 connector Power Input The following figure shows the input power specifications The power supply has a manual switch to select the correct input voltage Power Output The power supply outputs shown in the following figures include the current supply capability of all the connectors including system board DASD PCI and auxiliary outputs The total combined 3 3...

Страница 27: ...urrent Regulation Limits 3 3 V DC 3000 mA 5 0 to 5 0 5 0 V DC 4000 mA 5 0 to 4 0 12 0 V DC 25 0 mA 5 0 to 5 0 12 0 V DC 25 0 mA 10 0 to 9 0 Figure 15 Keyboard Port Supply Voltage Maximum Current Regulation Limits 5 0 V DC 275 mA 5 0 to 4 0 Figure 16 Auxiliary Device Port Supply Voltage Maximum Current Regulation Limits 5 0 V DC 300 mA 5 0 to 4 0 Figure 17 ISA Bus Adapters Per Slot Supply Voltage M...

Страница 28: ...ormal operation only after the fault has been removed and the power switch has been turned off for at least one second If an overvoltage fault occurs in the power supply the power supply latches all DC outputs into a shutdown state before any output exceeds 130 of the nominal value of the power supply Connector Description The power supply for the PC 300GL has four 4 pin connectors for internal de...

Страница 29: ...t Alternate Startup Sequence IBM Look and Feel Screen arrangements etc ACPI Advanced Configuration and Power Interfaces IDE Logical Block Addressing LBA support LSA 2 0 support Bootable CD ROM support LS120 support DM BIOS 2 1 DMI 2 0 compliant PC98 compliant Plug and Play Support for Plug and Play conforms to the following Plug and Play BIOS Specification 1 1a and 1 0 Plug and Play BIOS Extension...

Страница 30: ...onfiguration and Power Interface ACPI BIOS mode is enabled the operating system is allowed to control the power management features of your computer and the settings for APM BIOS mode are ignored Not all operating systems support ACPI BIOS mode Refer to your operating system documentation to determine if ACPI is supported Flash Update Utility Program The flash update utility program is a stand alo...

Страница 31: ...e computer where UMA is installed to remotely manage and monitor your computer UMA can also integrate into a number of server based management programs such as IBM Netfinity Manager enterprise management systems such as Tivoli TME 10 Tivoli NetView and Microsoft System Management Server SMS and Microsoft Management Console MMC Additionally you can configure the UMA program to forward simple networ...

Страница 32: ... 1 Parallel 2 and Parallel 3 in compatibility mode Use the above information to develop application programs Whenever possible use the BIOS as an interface to hardware to provide maximum compatibility and portability of applications among systems Hardware Interrupts Hardware interrupts are level sensitive for PCI interrupts and edge sensitive for ISA interrupts The interrupt controller clears its ...

Страница 33: ...he IRQ2 request Diskette Drives and Controller The following figures show the reading writing and formatting capabilities of each type of diskette drive Notes 1 Do not use either a 250 500 KB or 300 500 KB diskette drive for 5 25 inch diskettes that are designed for the 1 2MB mode 2 Low density 5 25 inch diskettes that are written to or formatted by a high capacity 1 2 MB diskette drive can be rel...

Страница 34: ...es must set the track to track access time for the different types of media that are used in the drives Diskette change signal Copy protection might not be able to reset this signal Write current control Copy protection that uses write current control does not work because the controller selects the proper write current for the media that is being used 26 Technical Information Manual ...

Страница 35: ...utines must daisy chain interrupts Each routine must check the function value and if it is not in the range of function calls for that routine it must transfer control to the next routine in the chain Because software interrupts are initially pointed to address 0 0 before daisy chaining check for this case If the next routine is pointed to address 0 0 and the function call is out of range the appr...

Страница 36: ...n ground NA 8 Blue ground NA 9 5 V used by DDC2B NA 10 Ground NA 11 Monitor ID 0 Not used I 12 DDC2B serial data I O 13 Horizontal sync O 14 Vertical sync O 15 DDC2B clock I O Figure 25 Page 1 of 3 System Memory Connector Pin Assignments Pin x64 Non Parity x72 ECC Pin x64 Non Parity x72 ECC 1 VSS VSS 85 VSS VSS 2 DQ0 DQ0 86 DQ32 DQ32 3 DQ1 DQ1 87 DQ33 DQ33 4 DQ2 DQ2 88 DQ34 DQ34 5 DQ3 DQ3 89 DQ35 ...

Страница 37: ...E0 111 CAS CAS 28 DQMB0 DQMB0 112 DQMB4 DQMB4 29 DQMB1 DQMB1 113 DQMB5 DQMB5 30 S0 S0 114 NC S1 31 DU NC 115 RAS RAS 32 VSS VSS 116 VSS VSS 33 A0 A0 117 A1 A1 34 A2 A2 118 A3 A3 35 A4 A4 119 A5 A5 36 A6 A6 120 A7 A7 37 A8 A8 121 A9 A9 38 A10 AP A10 AP 122 BA0 BA0 39 NC BA1 123 NC A11 40 VCC VCC 124 VCC VCC 41 VCC VCC 125 CK1 CK1 42 CK0 CK0 126 A12 A12 43 VSS VSS 127 VSS VSS 44 DU NC 128 CKE0 CKE0 ...

Страница 38: ...7 71 DQ26 DQ26 155 DQ58 DQ58 72 DQ27 DQ27 156 DQ59 DQ59 73 VCC VCC 157 VCC VCC 74 DQ28 DQ28 158 DQ60 DQ60 75 DQ29 DQ29 159 DQ61 DQ61 76 DQ30 DQ30 160 DQ62 DQ62 77 DQ31 DQ31 161 DQ63 DQ63 78 VSS VSS 162 VSS VSS 79 CK2 CK2 163 CK3 CK3 80 NC NC 164 NC NC 81 NC NC 165 SA0 SA0 82 SDA SDA 166 SA1 SA1 83 SCL SCL 167 SA2 SA2 84 VCC VCC 168 VCC VCC Figure 26 Page 1 of 3 System Memory Connector Pin Input Ou...

Страница 39: ...A 109 NC N A 26 VDD N A 110 VDD N A 27 WE I 111 CAS N A 28 DQMB0 I 112 DQMB4 I 29 DQMB1 I 113 DQMB4 I 30 S0 I 114 S1 I 31 OE0 i 115 RAS N A 32 GND N A 116 GND N A 33 A0 I 117 A1 I 34 A2 I 118 A3 I 35 A4 I 119 A5 I 36 A6 I 120 A7 I 37 A8 I 121 A9 I 38 A10 AP I 122 A11 I 39 NC BA1 123 NC A11 40 VDD N A 124 VDD N A 41 NC N A 125 CK1 N A 42 CK0 N A 126 A14 O 43 GND N A 127 GND N A 44 OE2 I 128 CKE0 N ...

Страница 40: ...65 MD21 I O 149 MD53 I O 66 MD22 I O 150 MD54 I O 67 MD23 I O 151 MD55 I O 68 GND N A 152 GND N A 69 MD24 I O 153 MD56 I O 70 MD25 I O 154 MD57 I O 71 MD26 I O 155 MD58 I O 72 MD27 I O 156 MD59 I O 73 VDD N A 157 VDD N A 74 MD28 I O 158 MD60 I O 75 MD29 I O 159 MD61 I O 76 MD30 I O 160 MD62 I O 77 MD31 I O 161 MD63 I O 78 GND N A 162 GND N A 79 CK2 O 163 CK3 O 80 NC N A 164 NC N A 81 NC O 165 SA0 ...

Страница 41: ...18 SA13 I O B19 REFRESH I O A19 SA12 I O B20 CLK O A20 SA11 I O B21 IRQ7 I A21 SA10 I O B22 IRQ6 I A22 SA9 I O B23 IRQ5 I A23 SA8 I O B24 IRQ4 I A24 SA7 I O B25 IRQ3 I A25 SA6 I O B26 DACK2 O A26 SA5 I O B27 TC O A27 SA4 I O B28 BALE O A28 SA3 I O B29 5 V DC NA A29 SA2 I O B30 OSC O A30 SA1 I O B31 Ground NA A31 SA0 I O D1 MEMCS16 I C1 SBHE I O D2 IOCS16 I C2 LA23 I O D3 IRQ10 I C3 LA22 I O D4 IRQ...

Страница 42: ... A7 INTC I B7 INTB I A8 5 V DC NA B8 INTD I A9 Reserved NA B9 PRSNT1 I A10 5 V DC I O NA B10 Reserved NA A11 Reserved NA B11 PRSNT2 I A12 Ground NA B12 Ground NA A13 Ground NA B13 Ground NA A14 Reserved NA B14 Reserved NA A15 RST O B15 Ground NA A16 5 V DC I O NA B16 CLK O A17 GNT O B17 Ground NA A18 Ground NA B18 REQ I A19 PCIPME NA B19 5 V DC I O NA A20 Address Data 30 I O B20 Address Data 31 I ...

Страница 43: ...41 3 3 V DC NA A42 Ground NA B42 SERR I O A43 3 3 V DC NA B43 3 3 V DC NA A44 C BE 1 I O B44 C BE 1 I O A45 Address Data 14 I O B45 Address Data 14 I O A46 Ground NA B46 Ground NA A47 Address Data 12 I O B47 Address Data 12 I O A48 Address Data 10 I O B48 Address Data 10 I O A49 Ground NA B49 Ground NA A50 Key NA B50 Key NA A51 Key NA B51 Key NA A52 Address Data 8 I O B52 Address Data 8 I O A53 Ad...

Страница 44: ...s bit 1 I O 35 SA0 O 16 Data bus bit 14 I O 36 SA2 O 17 Data bus bit 0 I O 37 CS0 O 18 Data bus bit 15 I O 38 CS1 O 19 Ground NA 39 Active I 20 Key Reserved NA 40 Ground NA Figure 31 Page 1 of 2 Diskette Drive Connector Pin Assignments Pin Signal I O Pin Signal I O 1 Drive 2 installed I 2 High density select O 3 Not connected NA 4 Not connected NA 5 Ground NA 6 Data rate 0 NA 7 Ground NA 8 Index I...

Страница 45: ...Pin Signal Name 1 3 3 V 11 3 3 V 2 3 3 V 12 12 V 3 Ground 13 Ground 4 5 V 14 ON OFF 5 Ground 15 Ground 6 5 V 16 Ground 7 Ground 17 Ground 8 PWR GOOD 18 Reserved 9 5 V AUX 19 5 V 10 12 V 20 5 V Figure 33 J13 Modem Ring Wakeup Connector Pin Assignments Pin Description 1 Internal Modem Wake Up on Ring 2 Ground Figure 34 J22 Wake on LAN Connector Pin Assignments Pin Description 1 5v AUX 2 Ground 3 Int...

Страница 46: ...3 Ground NA 4 5 V DC NA 5 Clock I O 6 Reserved NA Figure 37 Keyboard Port Connector Pin Assignments Pin Signal I O Pin Signal I O 1 Keyboard Data I O 2 Mouse Data I O 3 Ground NA 4 5 V DC NA 5 Keyboard Clock I O 6 Mouse Clock I O Figure 38 Serial Port Connector Pin Assignments Pin Signal I O Pin Signal I O 1 Data carrier detect I 2 Receive data I 3 Transmit data O 4 Data terminal read O 5 Ground N...

Страница 47: ...3 SLCT I 14 AUTO FD XT O 15 ERROR I 16 INIT O 17 SLCT IN O 18 Ground NA 19 Ground NA 20 Ground NA 21 Ground NA 22 Ground NA 23 Ground NA 24 Ground NA 25 Ground NA Figure 40 Joystick MIDI Connector Pin Assignments Pin Signal I O 1 5 V N A 2 Joystick A Button 1 I 3 Joystick A X Position I 4 Ground N A 5 Ground N A 6 Joystick A Y Position I 7 Joystick A Button 2 I 8 5 V N A 9 5 V N A 10 Joystick B Bu...

Страница 48: ... K C8000 DFFFF 96 KB PCI ISA space available to adapter ROMs 896 K 1 MB E0000 FFFFF 128 KB System ROM BIOS ISA Bus main memory shadowed 1 MB 16 MB 100000 FFFFFF 15 MB PCI ISA Space 16 MB 4095 872 MB 1000000 FFDFFFF 4079 8 MB PCI Space positive decode FFFE0000 FFFFFFFF 128 KB System ROM BIOS ISA Bus Figure 42 Page 1 of 3 I O Address Map Address Hex Size Description 0000 000F 16 bytes DMA 1 0010 001...

Страница 49: ...ial port 3 or 4 0228 0277 80 bytes General I O locations available to ISA bus 0278 027F 8 bytes SMC 27C673 LPT3 0280 02E7 102 bytes Available 02E8 02EF 8 bytes SMC PC37C673 Serial port 3 or 4 02F8 02FF 8 bytes COM2 0338 033F 8 bytes SMC PC37C673 Serial port 3 or 4 0340 036F 48 bytes Available 0370 0371 2 bytes SMC SIO planar Plug n Play index data registers 0372 0375 4 bytes Available 0376 0377 2 ...

Страница 50: ...nsfer Count register 00 15 Yes 0006 Channel 3 Memory Address register 00 15 Yes 0007 Channel 3 Transfer Count register 00 15 Yes 0008 Channels 0 3 Read Status Write Command register 00 07 0009 Channels 0 3 Write Request register 00 02 000A Channels 0 3 Write Single Mask register bits 00 02 000B Channels 0 3 Mode register write 00 07 000C Channels 0 3 Clear byte pointer write N A 000D Channels 0 3 ...

Страница 51: ...e Mask register bit 00 02 00D6 Channels 4 7 Mode register write 00 07 00D8 Channels 4 7 Clear byte pointer write N A 00DA Channels 4 7 Master clear write temp read 00 07 00DC Channels 4 7 Clear Mask register write 00 03 00DE Channels 4 7 Write All Mask register bits 00 03 00DF Channels 5 7 8 or 16 bit mode select 00 07 Bus Number hex Device Number hex Function Number hex Description 00 00 00 Intel...

Страница 52: ...interrupt from slave PIC 3 Available to user 4 COM1 5 5 LPT2 Audio if present 6 Diskette controller 7 LPT1 5 8 Real time clock 9 Video 10 Available to user 11 Available to user 12 Mouse port 13 Reserved math coprocessor 14 Primary IDE if present 15 Secondary IDE if present Figure 45 DMA Channel Assignments DMA Channel Data Width System Resource 0 8 bits Open 1 8 bits Open 2 8 bits Diskette drive 3...

Страница 53: ...al POST Error Codes POST error messages appear when POST finds problems with the hardware during power on or when a change in the hardware configuration is found POST error messages are 3 4 5 8 or 12 character alphanumeric messages Beep Codes A complete list of beep codes is provided in Hardware Maintenance Manual Copyright IBM Corp November 1998 45 ...

Страница 54: ... you any license to these patents You can send license inquiries in writing to IBM Director of Licensing IBM Corporation North Castle Drive Armonk NY 10504 1785 U S A Any references in this publication to non IBM Web sites are provided for convenience only and do not in any manner serve as an endorsement of those Web sites The materials at those Web sites are not part of the materials for this IBM...

Страница 55: ...ocessor and Peripheral Component Literature Source Intel Corporation PCI BIOS Specification 2 0 Source PCI Special Interest Group PCI Local Bus Specification 2 1 Source PCI Special Interest Group Plug and Play BIOS Specification 1 1 Source Microsoft Corporation available at http www microsoft com hwdev Plug and Play BIOS Specification Errata and Clarifications 1 0 Source Microsoft Corporation Univ...

Страница 56: ...AN 37 controller diskette drive 10 25 I O 10 keyboard mouse 11 parallel 11 serial 10 copy protection 25 D diagnostic program 22 DIMM connectors 5 diskette drive change signal 26 compatibility 25 controller 10 write current 26 write protect switch 14 diskette drives 25 DMA direct memory access channel assignments 44 E environment operating 16 error codes POST 45 Ethernet port 11 F fault overvoltage...

Страница 57: ...0 POST 21 40 POST error codes 45 power consumption 22 description 18 for components 19 power continued load currents 19 management modes 22 output protection 20 outputs 19 protection power supply 20 publications related vii R RAM random access memory 40 random access memory RAM 40 references 47 related information vii reserved areas vii S S3 Trio3D SVGA Super Video Graphics Array 8 SDRAM synchrono...

Страница 58: ...Index Wake Up on Ring 2 write current diskette 26 write protect switch diskette drive 14 50 Technical Information Manual ...

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