IBM PC 100, Техническое руководство

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Chapter 4. System Compatibility
Hardware Compatibility
This section briefly discusses hardware, software, and BIOS compatibility issues that must be considered
when designing application programs.
Many of the interfaces are the same as those used by the IBM Personal Computer AT. In most cases,
the command and status organization of these interfaces is maintained.
The functional interfaces are compatible with the following interfaces:
Ÿ
The Intel 8259 interrupt controllers (edge-triggered mode).
Ÿ
The National Semiconductor NS16450 and NS16550A serial communication controllers.
Ÿ
The Motorola MC146818 Time of Day Clock command and status (CMOS reorganized).
Ÿ
The Intel 8254 timer, driven from a 1.193 MHz clock (channels 0, 1, and 2).
Ÿ
The Intel 8237 DMA controller, except for the Command and Request registers and the Rotate and
Mask functions. The Mode register is partially supported.
Ÿ
The Intel 8272 or 82077 diskette drive controllers.
Ÿ
The Intel 8042 keyboard controller at addresses 0060h and 0064h.
Ÿ
All video standards using VGA, EGA, CGA, MDA, and Hercules modes.
Ÿ
The parallel printer ports (Parallel 1, Parallel 2, and Parallel 3) in compatibility mode.
Use the following information to develop application programs for personal computer products. Whenever
possible, use the BIOS as an interface to hardware to provide maximum compatibility and portability of
applications among systems.
Hardware Interrupts
Hardware interrupts are level sensitive for PCI interrupts and edge sensitive for ISA interrupts. The
interrupt controller clears its in-service register bit when the interrupt routine sends an End-of-Interrupt
(EOI) command to the controller. The EOI command is sent regardless of whether the incoming interrupt
request to the controller is active or inactive.
The interrupt-in-progress latch is readable at an I/O-address bit position. This latch is read during the
interrupt service routine and might be reset by the read operation, or it might require an explicit reset.
Note: For performance and latency considerations, designers might want to limit the number of devices
sharing an interrupt level.
With level-sensitive interrupts, the interrupt controller requires that the interrupt request be inactive at the
time the EOI command is sent; otherwise, a new interrupt request will be detected. To avoid this, a
level-sensitive interrupt handler must clear the interrupt condition (usually by a read or write operation to
an I/O port on the device causing the interrupt). After processing the interrupt, the interrupt handler:
1. Clears the interrupt
2. Waits one I/O delay
3. Sends the EOI
4. Waits one I/O delay
5. Enables the interrupt through the Set Interrupt Enable Flag command
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Technical Information Manual