Chapter 2. Architecture and technical overview
25
2.9 Service processor
The service processor is an embedded controller based on a PowerPC 405GP processor
(PPC405) implementation running the service processor internal operating system. The
service processor operating system contains specific programs and device drivers for the
service processor hardware.
The key components include a flexible service processor-base (FSP-B) and an extender
chipset (FSP-E). Figure 2-10 illustrates the service processor.
Figure 2-10 Service processor block diagram
The flexible service processor core is a five-stage pipeline instruction processor and contains
32-bit general purpose registers. The flash ROM contains a compressed image of a software
load.
Service processor
block diagram
Base
(FSP-B)
DS
1-wire
Rack Ind Conn
Flash ROM
40 MB or48 MB
SRAM
1 MB
NVRAM
Controller
DDR Interface
Flash
NVRAM
Interface
UART
#2
UART
#1
UART
#3
UART
#4
Broadcom
PHY
RJ-45
RJ-45
Enet #1
Enet # 2
ALE
DDR
64 MB
I2C
Engines
4 I2C
Engines
JTAG
Engines
2 JTAG
Engines
RTC
32.768 KHz
OSC
INTR
8
Interrupts
PCI-X at 100 MHz
Extender
(FSP-E)
UART #1-2,
7-9
I2C
Engines
6 I2C Engines
JTAG
Engines
8 JTAG Engines
INTR
5 Interrupts
UART #3
UART #4
UART #3
UART #5, Port0
UART #6
To Smartchip VPD Serial
MUX
GPIO
GPIO
HMC
Ports
TOD/SIT
4 MHz
OSC
RISC Watch
Conn
Secondary
PCI
Secondary
PCI
PCI Bus
MUX
X/R
X/R
PS1
XCVR
S2-rear
DB9
XCVR
S1-rear
DB9
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