IBM DYLA-28100 - Travelstar 8.1 GB Hard Drive, Технические характеристики

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6.4 Signal Description
DD00-DD15 16-bit bi-directional data bus between the host and the H D D . The lower 8 lines, DD00-07,
are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer.
These are Three-State lines that have a 24 mA current sink capability.
DA00-DA02 Address used to select the individual register in the H D D .
-CS0 Chip select signal generated from the Host address bus. When active, one of the Command
Block Registers (Data, Error{Features when written}, Sector Count, Sector Number, Cyl-
inder Low, Cylinder High, Drive/Head and Status{Command when written} register) can be
selected.
(SeeFigure 36 on page 54 .)
-CS1 Chip select signal generated from the Host address bus. When active, one of the Control
Block Registers (Alternate Status{Device Control when written} and Drive Address register)
can be selected.
(SeeFigure 36 on page 54 .)
-RESET This line is used to reset the H D D . It shall be kept at a Low logic state during power up
and kept High thereafter for normal operation.
-DIOW The rising edge clocks data from the host data bus to a register or data register of the H D D .
-DIOR When low, this signal enables data from a register or data register of the drive onto data bus.
The data on the bus shall be latched on the rising edge of -DIOR.
INTRQ Interrupt is enabled only when the drive is selected, and the host activates the -IEN bit in
the Device Control Reg. Otherwise, this signal is in high impedance state regardless of the
state of the I R Q bit. The interrupt is set when the I R Q bit is set by the drive CPU. I R Q is
reset to zero by a host read of the status register or a write to the Command Reg. This
signal is a 3-State line with 24 mA sink capability.
IORDY Indication to host that the drive is ready to complete current I/O cycle. This line is driven
low at the falling edge of -DIOR or -DIOW, when H D D needs some additional WAIT
cycle(s) to extend PIO cycle. This line can be connected to host I O R D Y signal in order to
insert WAIT state(s) in the host PIO cycle. This is an Open-Drain output with 24 mA sink
capability.
CSEL This signal is monitored to determine the drive address, Device-0 (Master) or Device-1
(Slave), when the jumper on the interface connector is at Position-3. (Refer to Figure 35 on
page 53 for jumper position.)
When CSEL is ground or at a low level, the H D D works as a Device-0 (Master). If CSEL is
open or a high level, the H D D works as a Device-1 (Slave).
The signal level of CSEL to one H D D should be different from the signal level to another
H D D on the same AT interface cable, to avoid Device-0 (master) - Device-0 (master) or
Device-1 (slave) - Device-1 (slave) configurations.
Signal level of CSEL should be constant while HDD(s) are on the AT interface.
-HIOCS16 Indication to the host that 16-bit wide data register has been addressed and that the drive is
prepared to send or receive a 16-bit wide data word. This signal is an Open-Drain output
with 24 mA sink capability and an external resistor is needed to pull this line to 5 Volt.
-DASP This is a time-multiplexed signal which indicates that a drive is active, or that device 1 is
present. This signal is driven by an Open Collector driver and internally pulled-up to 5 Volt
through 10Kohm resistor.
During Power-On initialization or after -RESET is negated, -DASP shall be asserted by
Device 1 within 400 msec to indicate that device 1 is present.
Device 0 shall allow up to
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O E M Specifications of DYLA-2xxxx 2.5 inch H D D