IBM DBCA-203240, Технические характеристики

Страница: 97 / 190

11.0 Command Protocol
The commands are grouped into different classes according to the protocols followed for command exe-
cution. The command classes with their associated protocols are defined below.
For all commands, the host must first check if B S Y = 1 , and should proceed no further unless and until
B S Y = 0 . For all commands, the host must also wait for R D Y = 1 before proceeding.
A device must maintain either B S Y = 1 or D R Q = 1 at all times until the command is completed. The
I N T R Q signal is used by the device to signal most, but not all, times when the BSY bit is changed from 1 to
0 during command execution.
A command shall only be interrupted with a hardware or software reset. The result of writing to the
Command register while B S Y = 1 or D R Q = 1 is unpredictable and may result in data corruption. A
command should only be interrupted by a reset at times when the host thinks there may be a problem, such
as a device that is no longer responding.
Interrupts are cleared when the host reads the Status Register, issues a reset, or writes to the Command
Register.
Figure 113 on page 173 shows the device timeout values.
11.1 Data In Commands
These commands are:
Identify Device
Read Buffer
Read Long
Read Multiple
Read Sectors
S M A R T Read Attribute Values
S M A R T Read Attribute Thresholds
Execution includes the transfer of one or more 512 byte ( > 5 1 2 bytes on Read Long) sectors of data from
the device to the host.
1. The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and
Device/Head Registers.
2. The host writes the command code to the Command Register.
3. For each sector (or block) of data to be transferred:
a. The device sets B S Y = 1 and prepares for data transfer.
b. When a sector (or block) of data is available for transfer to the host, the device sets B S Y = 0 , sets
D R Q = 1 , and interrupts the host.
c. In response to the interrupt, the host reads the Status Register.
d. The device clears the interrupt in response to the Status Register being read.
e. The host reads one sector (or block) of data via the Data Register.

Copyright IBM Corp. 1998
89