IBM CPC700, Руководство пользователя

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CPC700 User’s Manual—Preliminary 3-17
3.12 PLB Slave Interface to Memory (PCI to Memory)
The processor interface’s PLB Slave interface allows the PCI bus to access system memory. The PLB Slave
interface contains a single 32 byte write buffer for PCI to memory write cycles and a single 32 byte read
buffer for PCI to memory read cycles. Once the PCI has gained access to memory (via the internal memory
controller interface) for a given transfer, the memory is unavailable for subsequent PCI to memory transfers
or processor to memory transfers until the address tenure of the current access completes. In particular, a
PCI to memory burst transfer will not be interrupted for the sole purpose of servicing a pending processor
to memory read request.
Reads:
PCI to memory reads generate various sizes/types of doubleword requests to the memory controller. As a
result, the memory controller always returns a minimum of a full doubleword to the PLB Slave interface
which stores the data in the 32 byte read buffer for transfer onto the PLB bus. The PLB Slave interface per-
forms the necessary unpacking of data for byte, halfword, and word burst PLB transfers thus increasing the
available memory bandwidth for pending processor accesses.
Writes:
Write data from the PCI to memory is buffered in a 32 byte write buffer and, when possible, packed into 8
byte, doubleword aligned, transfers before being written to memory. PCI to memory write cycles are buff-
ered, not posted, thus eliminating the need to snoop the PCI to memory write buffer prior to processor ac-
cesses to system memory.
The 32 byte processor to memory posted write buffer is snooped, in addition to the processor's L1 cache,
prior to allowing the PCI bus to access system memory. PCI to memory burst transfers which cross a pro-
cessor cache line boundary will be delayed until the snoop response is known for the cache line being ac-
cessed. If the access hits in the L1 cache or the 60x to memory write buffer, the burst cycle will be terminated
and the processor/write buffer will be granted the bus to allow for the cast out. For register information, see
Sections 3.16.13, 3.16.14, and 3.16.17 in Section 3.16, ”Processor Interface Register Description”.
The following table lists the corresponding memory controller interface requests generated in response to
PCI requests (Read or Write) with the indicated size.
W - Word, DW - Double Word
Table 16. PLB to Memory Cycle Translation
PCI Interface Cycle Memory Controller I/F Request Snoop
1 - 8 Bytes DW w/byte enables 1 prior to MC request
4W Line 1 x 2 Beat DW (wrap) 1 prior to MC request
8W Line 1 x Quad DW (wrap) 1 prior to MC request
W Burst DW(s) and/or Quad DW(s) 1 per 32 byte boundary crossed