12-2
Processor Local Bus (PLB)
12.2 PLB Arbiter Registers
PLB arbiter registers are accessed using the addresses in Table 102.
12.2.1 PLB Arbiter Control Register (PACR)
The PACR controls PLB arbitration priority, which is determined by PLB priority mode and PLB priority
order.
12.2.2 PLB Error Address Register (PEAR)
The read-only PEAR contains the address of the access on which a bus timeout error occurred.
The PEAR can be locked by the master. Once locked, the PEAR cannot be updated, if a subsequent
error occurs, until all PESR[FLCKn] fields are cleared (n is the master ID).
Table 102. PLB Arbiter Registers
Mnemonic
Register Name
Address
Access
PACR
PLB Arbiter Control Register
0xFF50_085C
R/W
PEAR
PLB Error Address Register
0xFF50_0858
R/O
PESR
PLB Error Status Register
0xFF50_0850
R/Clear
Figure 65. PLB Arbiter Control Register (PACR)
0
PPM
PLB Priority Mode
0 Fixed
1 Fair
1:2
PPO
PLB Priority Order
00 Masters 0, 1
01 Masters 1, 0
10 Reserved
11 Reserved
3:31
Reserved
Figure 66. PLB Error Address Register (PEAR)
0:31
Address of bus timeout error
0
1
2
3
31
PPM
PPO
0
31
Содержание CPC700
Страница 1: ...CPC700 Memory Controller and PCI Bridge User s Manual Version 1 1 Issue Date 3 22 00 Preliminary...
Страница 10: ...Table of Contents x Table of Contents...
Страница 16: ...Tables xvi List of Tables...
Страница 28: ...1 12 CPC700 User s Manual Preliminary...
Страница 72: ...3 36 Processor Interface...
Страница 132: ...4 60 Memory Controller...
Страница 184: ...5 52 PCI Interface...
Страница 194: ...6 10 Clock Power Management and Reset...
Страница 224: ...8 18 IIC...
Страница 244: ...10 10 Interrupt Controller...
Страница 246: ...I 11 2 JTAG...
Страница 250: ...12 4 Processor Local Bus PLB...
Страница 262: ...14 10 Register Summary...
Страница 267: ...CPC700 User s Manual Preliminary...