IBM 6400 Series, Инструкция по техническому обслуживанию

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Data Controller
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Data Controller
The data controller (DC) consists of the following elements:
•
68EC030 microprocessor
•
Two flash SIMM sockets, used for up to 30MB of program memory
•
Two DRAM SIMM sockets, used for up to 32MB of data memory
•
8K x 8 Non-Volatile Battery-Backed static RAM (NVRAM) for storage of
configuration and system statistical data
•
VX ASIC (Application-Specific Integrated Circuit)
•
Host I/O Drivers/Termination
68EC030 Microprocessor
A Motorola** 68EC030 microprocessor serves as the processor of the DC
unit. This processor runs at 25 MHz on all models except the 6400-050, -P50,
-010, -P10, -015, -C05, and -C5P.
On 6400-050, -P50, -010, -P10, -015, -C05, and -C5P printers the 68EC030
processor runs at 40 MHz and the controller board on these models is called
the “CMX 040.” The CMX 040 controller is backward compatible with any
6400 Series printer, but must be used in 6400-050, -P50, -010, -P10, -015, -
C05, and -C5P printers.
Although this chapter refers to the DC microprocessor as simply the “030,”
remember that two different clock speeds are available.
Flash Memory
The DC stores program and emulation code in flash memory. Flash memory
is erasable, non-volatile, and significantly faster than a disk drive.
The DC uses AMD** 5.0V-only flash memory, which does not require higher
programming and erasing voltages on the board (it has an internal charge
pump to make these voltages itself). This memory supports at least 100,000
write/erase cycles. The flash memory is 32 bits wide. It is byte, word, and
double word readable, but is always written as double words.
Two 80-pin SIMM sockets are provided for flash memory. Up to 30MB of flash
(total), organized as up to four banks, may be installed in the two sockets on
the controller board. The boot code for the 68EC030 processor must reside in
bank 0.
Programs stored in flash memory are changed through the parallel or serial
port.
DRAM
System DRAM is used for program variables, image buffers, and input
buffers. All DRAM supports page mode operation and is addressable by
individual byte.
Two standard 72-pin DRAM SIMMs are used for expansion memory. The DC,
through the VX ASIC, may address up to 32MB of DRAM in four banks.