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COM Express® Carrier Board Design Guide

Signal

Pin#

Description

I/O

Remarks

P
PEG_RX12-

C91
C92

PEG channel 12, Receive
Input differential pair.

I PCIE

P
PEG_TX12-

D91
D92

PEG channel 12, Transmit
Output differential pair.

O PCIE

P
PEG_RX13-

C94
C95

PEG channel 13, Receive
Input differential pair.

I PCIE

P
PEG_TX13-

D94
D95

PEG channel 13 Transmit
Output differential pair.

O PCIE

P
PEG_RX14-

C98
C99

PEG channel 14, Receive
Input differential pair.

I PCIE

P
PEG_TX14-

D98
D99

PEG channel 14, Transmit
Output differential pair.

O PCIE

P
PEG_RX15-

C101
C102

PEG channel 15, Receive
Input differential pair.

I PCIE

P
PEG_TX15-

D101
D102

PEG channel 15, Transmit
Output differential pair.

O PCIE

SDVO_I2C_CLK

D73

I2C based control signal
(clock) for SDVO device.

O 2.5V
CMOS

SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only)

SDVO_I2C_DATA

C73

I2C based control signal
(data) for SDVO device

I/O 2.5V
OD CMOS

SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only)

PEG_LANE_RV#

D54

PCI Express Graphics lane
reversal input strap. Pull
low on the carrier board to
reverse lane order.

I 3.3V
CMOS

PEG_ENABLE#

D97

PEG enable function.
Strap to enable PCI
Express x16 external
graphics interface. Pull
low to disable internal
graphics and enable the
x16 interface.

I 3.3V
CMOS

Type 2 only

PCIE_
PCIE_CLK_REF-

A88
A89

PCIe Reference Clock for
all COM Express PCIe
lanes, and for PEG lanes

O CMOS

COM Express only allocates a
single reference clock

Содержание ET976

Страница 1: ...COM EXPRESS CARRIER BOARD DESIGN GUIDE Version 1 0 January 2022...

Страница 2: ...antee this document is error free IBASE assumes no liability for incidental or consequential damages arising from misapplication or inability to use the information contained herein nor for any infrin...

Страница 3: ...3 1 DisplayPort HDMI DVI 11 2 3 1 1 Reference Schematic 12 2 3 1 2 Routing Considerations 17 2 3 2 SDVO 18 2 3 2 1 Signal Definitions 18 2 3 2 2 Reference Schematics 18 2 3 2 3 Routing Considerations...

Страница 4: ...dio Interfaces 40 2 11 1 Reference Schematics 41 2 11 1 1 High Definition Audio 41 2 11 2 Routing Considerations 43 2 12 LPC Bus Low Pin Count Interface 44 2 12 1 Signal Definition 44 2 12 2 LPC Bus R...

Страница 5: ...61 2 18 3 Power Management Signals 62 2 18 4 Watchdog Timer 65 2 18 5 General Purpose Input Output GPIO 65 2 18 6 Fan Connector 66 2 18 7 Thermal Interface 67 2 19 PCI Bus 68 2 19 1 Signal Definition...

Страница 6: ...vi COM Express Carrier Board Design Guide 5 5 COM Express Connector Tyco This page is intentionally left blank...

Страница 7: ...is given The examples shown here have been taken from the designs that were already tested For any questions that you may have in the design of carrier boards please contact IBASE sales representative...

Страница 8: ...Express Graphics Digital Display Interfaces LAN USB Ports USB 3 0 SATA LVDS Embedded DisplayPort eDP VGA Digital Audio Interfaces LPC Bus Low Pin Count Interface Serial Peripheral Interface Bus Genera...

Страница 9: ...General Purpose PCIe Lanes 2 1 1 Device Up Device Down and PCIe Rx Tx Coupling Capacitors Figure 1 PCIe Rx Coupling Capacitors The coupling caps for the Module PCIe TX lines are to be on the Module a...

Страница 10: ...4 COM Express Carrier Board Design Guide 2 1 2 Schematic Examples Figure 2 PCI Express x1 Slot Example...

Страница 11: ...COM Express Carrier Board Design Guide 5 Figure 3 PCI Express x4 Slot Example...

Страница 12: ...6 COM Express Carrier Board Design Guide Figure 4 PCIe Mini Card Reference Circuitry...

Страница 13: ...used 92 10 differential impedance Gen1 designs used 100 20 differential impedance New designs use 85 15 differential impedance for Gen1 Gen2 and Gen3 signaling Route the traces as differential pairs r...

Страница 14: ...PCIE PEG_TX4 PEG_TX4 D65 D66 PEG channel 4 Transmit Output differential pair O PCIE Type 2 SDVOC_RED Shared with SDVOC_RED PEG_RX5 PEG_RX5 C68 C69 PEG channel 5 Receive Input differential pair I PCIE...

Страница 15: ...D101 D102 PEG channel 15 Transmit Output differential pair O PCIE SDVO_I2C_CLK D73 I2C based control signal clock for SDVO device O 2 5V CMOS SDVO enabled if this line is pulled up to 2 5V on Carrier...

Страница 16: ...10 COM Express Carrier Board Design Guide 2 2 1 Reference Schematics Figure 5 x1 x4 x8 x16 Slot...

Страница 17: ...auxiliary lane and 1 hot plug detect signal The DDC_AUX_SEL pin should be routed to pin 13 of the DisplayPort connector to enable Dual Mode When HDMI DVI is directly done on the Carrier Board this pi...

Страница 18: ...12 COM Express Carrier Board Design Guide 2 3 1 1 Reference Schematic Figure 6 DisplayPort Reference Schematics...

Страница 19: ...COM Express Carrier Board Design Guide 13 Figure 7 HDMI Example 1...

Страница 20: ...14 COM Express Carrier Board Design Guide Figure 7 HDMI Example 2...

Страница 21: ...COM Express Carrier Board Design Guide 15 Figure 8 DVI Example 1...

Страница 22: ...16 COM Express Carrier Board Design Guide Figure 8 DVI Example 2...

Страница 23: ...od TMDS The TDMS differential signals between the level shifter and the DVI connector have to be routed in pairs with a differential impedance of 100 The length of the differential signals must be kep...

Страница 24: ...G COM Express Carrier Board Design Guide Rev 2 0 December 6 2013 Page 59 Figure 22 DVI Example 2 3 2 3 Routing Considerations DVI is based on the differential signaling method TDMS The TDMS differenti...

Страница 25: ...on I O Remarks GBE0_MDI0 GBE0_MDI0 A13 A12 Media Dependent Interface MDI differential pair 0 The MDI can operate in 1000 100 and 10Mbit sec modes I O GBE This signal pair is used for all modes GBE0_MD...

Страница 26: ...to meet a specific waveform template and associated signal integrity requirements defined in the IEEE 802 3 2005 specification Routing rules should be observed on the Carrier Board The four status sig...

Страница 27: ...ule USB4 A40 USB Port 4 data or D I O USB optional on Module USB4 A39 USB Port 4 data or D I O USB optional on Module USB5 B40 USB Port 5 data or D I O USB optional on Module USB5 B39 USB Port 5 data...

Страница 28: ...e USB signals as differential pairs with a 90 differential impedance and a 45 single ended impedance A USB pair is routed on a single layer adjacent to a ground plane USB pairs should not cross plane...

Страница 29: ...B channels 2 and 3 I CMOS Table 7 USB 3 0 Differential Lines Signal Pins Pins Description I O USB_SSTX0 D4 B23 USB Port 0 SuperSpeed TX O PCIE USB_SSTX0 D3 B22 USB Port 0 SuperSpeed TX O PCIE USB_SSTX...

Страница 30: ...24 COM Express Carrier Board Design Guide 2 6 2 Reference Schematics Figure 12 USB 3 0 Example 1...

Страница 31: ...COM Express Carrier Board Design Guide 25 Figure 12 USB 3 0 Example 2...

Страница 32: ...ended impedance Route USB SuperSpeed signals as differential pairs with an 85 differential impedance and a 50 single ended impedance A USB pair is routed on a single layer adjacent to a ground plane U...

Страница 33: ...tial pair I SATA SATA1_TX SATA1_TX B16 B17 Serial ATA channel 1 Transmit output differential pair O SATA SATA2_RX SATA2_RX A25 A26 Serial ATA channel 2 Receive input differential pair I SATA SATA2_TX...

Страница 34: ...ions Route SATA signals as differential pairs with an 85 differential impedance and a 50 single ended impedance Ideally a SATA pair is routed on a single layer adjacent to a ground plane SATA pairs sh...

Страница 35: ...nnel B differential signal pair 0 O LVDS LVDS_B1 LVDS_B1 B73 B74 LVDS channel B differential signal pair 1 O LVDS LVDS_B2 LVDS_B2 B75 B76 LVDS channel B differential signal pair 2 O LVDS LVDS_B3 LVDS_...

Страница 36: ...30 COM Express Carrier Board Design Guide 2 8 2 Reference Schematics Figure 14 LVDS Reference Schematic 1...

Страница 37: ...COM Express Carrier Board Design Guide 31 Figure 14 LVDS Reference Schematic 2...

Страница 38: ...to a ground plane LVDS pairs should not cross plane splits Keep layer transitions to a minimum When needed reference LVDS pairs to a power plane The power plane must be well bypassed Length matching b...

Страница 39: ...iption I O eDP_TX0 A75 eDP lane 0 TX O PCIe eDP_TX0 A76 eDP lane 0 TX O PCIe eDP_TX1 A73 eDP lane 1 TX O PCIe eDP_TX1 A74 eDP lane 1 TX O PCIe eDP_TX2 A71 eDP lane 2 TX O PCIe eDP_TX2 A72 eDP lane 2 T...

Страница 40: ...34 COM Express Carrier Board Design Guide 2 9 2 Reference Schematics Figure 15 eDP Reference Schematic...

Страница 41: ...ore the signal is actively driven The panel control signals eDP_BLKT_EN eDP_BLKT_CTRL as well as eDP_HPD are 3 3V level signals Pay attention to your panel specifications for correct voltage levels an...

Страница 42: ...g output VGA_BLU B92 3 Blue component of analog DAC monitor output designed to drive a 37 5 equivalent load O Analog Analog output VGA_HSYNC B93 13 Horizontal sync output to VGA monitor O 3 3V CMOS VG...

Страница 43: ...COM Express Carrier Board Design Guide 37 2 10 2 VGA Reference Schematics Figure 16 VGA Reference Schematics 1...

Страница 44: ...38 COM Express Carrier Board Design Guide Figure 16 VGA Reference Schematics 2...

Страница 45: ...ls with 5V tolerance so implement high impedance unidirectional buffers to prevent potential electrical over stress of the Module and avoid that VGA monitors may attempt to drive the monitor sync sign...

Страница 46: ...3V Suspend CMOS AC HDA_SYNC A29 Serial Sample Rate Synchronization O 3 3V CMOS AC HDA_BITCLK A32 24 MHz Serial Bit Clock for HDA CODEC O 3 3V CMOS AC HDA_SDOUT A33 Audio Serial Data Output Stream O 3...

Страница 47: ...COM Express Carrier Board Design Guide 41 2 11 1 Reference Schematics 2 11 1 1 High Definition Audio Figure 18 HDA Example Schematic 1...

Страница 48: ...42 COM Express Carrier Board Design Guide Figure 18 HDA Example Schematic 2...

Страница 49: ...e analog ground plane The split between the planes must be at least 0 05 inch wide Route analog power and signal traces over the analog ground plane Route digital power and signal traces over the digi...

Страница 50: ...ized IRQ I O 3 3V CMOS LPC_FRAME B3 LPC frame indicates start of a new cycle or termination of a broken cycle O 3 3V CMOS LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 B4 B5 B6 B7 LPC multiplexed command address an...

Страница 51: ...COM Express Carrier Board Design Guide 45 2 12 2 LPC Bus Reference Schematics 2 12 2 1 Super I O Figure 19 LPC Super I O Example 1...

Страница 52: ...46 COM Express Carrier Board Design Guide Figure 19 LPC Super I O Example 2...

Страница 53: ...milar to PCI signals Route the LPC bus as 55 single ended signals The bus preferably should be referenced to ground or to a well bypassed power plane or a combination of the two Point to point daisy c...

Страница 54: ...ier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Carriers shall use less than 100mA of SPI_POWER SPI_POWER shall only be used to power SPI devi...

Страница 55: ...9 2 13 2 SPI Reference Schematics Figure 21 SPI Reference Schematics 2 13 3 Routing Considerations The SPI signals SPI_MISO SPI_MOSI SPI_CS and SPI_CLK should be routed with a maximum length of 4 5 an...

Страница 56: ...line I O OD CMOS 3 3V Suspend 2 14 2 Reference Schematics Figure 22 System Configuration EEPROM Circuitry 2 14 3 Connectivity Considerations The maximum capacitance allowed on the Carrier General Pur...

Страница 57: ...COM Express Carrier Board Design Guide 51 2 15 System Management Bus SMBus Figure 23 System Management Bus Separation...

Страница 58: ...ta line I O OD CMOS 3 3V Suspend rail SMB_ALERT B15 System Management Bus Alert I CMOS 3 3V Suspend Rail 2 15 2 Routing Considerations The SMBus should be connected to all or none of the PCIe PCI devi...

Страница 59: ...gnal Definition Signal Pin Description I O SER0_TX A98 Transmit Line for Serial Port 0 O CMOS protected SER0_RX A99 Receive Line for Serial Port 0 I CMOS protected SER1_TX A101 Transmit Line for Seria...

Страница 60: ...54 COM Express Carrier Board Design Guide 2 16 2 Reference Schematics 2 16 2 1 General Purpose Serial Port Example Figure 24 General Purpose Serial Port Example 1...

Страница 61: ...COM Express Carrier Board Design Guide 55 Figure 24 General Purpose Serial Port Example 2...

Страница 62: ...ations that need to be taken 2 17 CAN Interface 2 17 1 Signal Definitions Table 17 CAN Interface Signal Definition Signal Pin Description I O CAN_TX A101 Transmit Line for CAN can be shared with SER1...

Страница 63: ...COM Express Carrier Board Design Guide 57 2 17 2 Reference Schematics Figure 25 CAN Bus Example 1...

Страница 64: ...hould be routed as a differential pair signal with 120 Ohm differential impedance The end points of CAN bus should be terminated with 120 Ohms or with 60 Ohms from the CAN_H line and 60 Ohms from the...

Страница 65: ...signal of the Module used by an external keyboard controller to force a system reset I 3 3V CMOS Only Available on T1 T5 KBD_A20GATE A87 Input signal of the Module used by an external keyboard control...

Страница 66: ...60 COM Express Carrier Board Design Guide 2 18 1 Speaker Output Figure 26 Speaker Output Circuitry...

Страница 67: ...COM Express Carrier Board Design Guide 61 2 18 2 RTC Battery Implementation Figure 27 RTC Battery Circuitry with Serial Schottky Diode...

Страница 68: ...he current system state and context is stored in main memory and all unnecessary system logic is turned off Only main memory and logic required to wake up the system remain powered by the Suspend volt...

Страница 69: ...operating voltages are within the ranges required for proper operation I 3 3V CMOS SUS_STAT B18 Suspend status signal to indicate that the system will be entering a low power state soon It can be use...

Страница 70: ...64 COM Express Carrier Board Design Guide Figure 28 PWRBTN and SYS_RESET Circuitry...

Страница 71: ...rpose input pins Pulled high internally on the Module I 3 3V CMOS GPI3 A85 General purpose input pins Pulled high internally on the Module I 3 3V CMOS GPO0 A93 General purpose output pins Upon a hardw...

Страница 72: ...66 COM Express Carrier Board Design Guide 2 18 6 Fan Connector Figure 31 Fan Connector Reference Schematic...

Страница 73: ...Thermal Alarm active low signal generated by the external hardware to indicate an over temperature situation This signal can be used to initiate thermal throttling I 3 3V CMOS THRMTRIP A35 Thermal Tr...

Страница 74: ...a lines I O 3 3V PCI_AD18 D38 PCI bus multiplexed address and data lines I O 3 3V PCI_AD19 C40 PCI bus multiplexed address and data lines I O 3 3V PCI_AD20 D39 PCI bus multiplexed address and data lin...

Страница 75: ...output line active low O 3 3V PCI_RESET C23 PCI Reset output active low O 3 3V_SBY Asserted during system reset PCI_LOCK C35 PCI Lock control line active low I O 3 3V PCI_SERR D33 System Error SERR ma...

Страница 76: ...CI Bus Interrupt Routing Device Signal Slot Device 1 Slot Device 2 Slot Device 3 Slot Device 4 IDSEL PCI_AD 20 PCI_AD 21 PCI_AD 22 PCI_AD 23 INTA PCI_IRQ A PCI_IRQ B PCI_IRQ C PCI_IRQ D INTB if used P...

Страница 77: ...Design Guide 71 2 19 3 1 Device Down Example Figure 33 PCI Device Down Example Dual UART Please refer to PICMG COM Express Carrier Board Design Guide Rev 2 0 December 6 2013 Page 150 Figure 60 PCI Dev...

Страница 78: ...C12 Bidirectional data to from IDE device I O 3 3V 16 16 30 IDE_D15 C5 Bidirectional data to from IDE device I O 3 3V 18 18 31 IDE_A 0 2 D13 D15 Address lines to IDE device O 3 3V 35 33 36 35 33 36 2...

Страница 79: ...rd Design Guide 73 Figure 34 IDE 40 Pin and CompactFlash 50 Pin Connector Please refer to PICMG COM Express Carrier Board Design Guide Rev 2 0 December 6 2013 Page 155 Figure 63 IDE 40 Pin and Compact...

Страница 80: ...74 COM Express Carrier Board Design Guide Chapter 3 Power and Reset The information provided in this chapter includes...

Страница 81: ...COM Express Carrier Board Design Guide 75 3 1 ATX Style Power Control 3 2 Reference Schematics Figure 35 AT and ATX Power Supply 1...

Страница 82: ...5V 3 3V and 12V outputs are all present and OK to use 12V1DC 12V power rail for use by all system components except for the CPU controlled by 12V2DC 12V power rail for use by the CPU controlled by PS_...

Страница 83: ...oad is recommended K eep the Carrier Board VCC_12 trace short wide and away from other parts of the Carrier Board If there are layer transitions in the power delivery path use redundant power vias via...

Страница 84: ...78 COM Express Carrier Board Design Guide Chapter 4 Carrier Board PCB Layout Guidelines...

Страница 85: ...igure 36 Four Layer Stack up The figure above is an example of a four layer stack up Layers L1 and L4 are used for signal routing Layers L2 and L3 are used for solid ground and power planes respective...

Страница 86: ...f a six layer stack up Layers L1 L3 L4 and L6 are used for signal routing Layers L2 and L5 are power and ground planes respectively Microstrips on Layers 1 and 6 reference solid ground and power plane...

Страница 87: ...e solid ground planes while L4 and L5 are used for power Microstrip Layers 1 and 8 reference solid ground planes on Layers 2 and 7 respectively Inner signal Layers 3 and 6 are asymmetric striplines th...

Страница 88: ...82 COM Express Carrier Board Design Guide 4 3 Trace Impedance Considerations Figure 39 Stackup Impedance...

Страница 89: ...M Express Carrier Board Design Guide 83 Chapter 5 Mechanical Considerations 5 1 Form Factors Figure 40 Mechanical comparison of available COM Express Form Factors All dimensions are shown in millimete...

Страница 90: ...84 COM Express Carrier Board Design Guide 5 2 Heatspreader Figure 41 IBASE HSET976 1 Heatspreader Figure 42 Side View of Heatspreader COM Express Module Carrier board layer...

Страница 91: ...COM Express Carrier Board Design Guide 85 5 3 COM Express Carrier Board Figure 43 IBASE IP413 COM Express Carrier Board...

Страница 92: ...86 COM Express Carrier Board Design Guide 5 4 COM Express Module and Heatsink Figure 44 IBASE ET976 and Heatsink...

Страница 93: ...COM Express Carrier Board Design Guide 87 5 5 COM Express Connector Tyco Figure 45 Tyco 220 pin COM Express Connector Pitch 0 5mm H 8mm...

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