Panel Specification
6.5 Power ON/OFF Sequence
VDD power and lamp on/off sequence are as follows. Interface signals are also shown in the chart. Signals
from any system shall be Hi-Z state or low level when VDD is off.
Value
Parameter
Min.
Typ.
Max.
Unit
]
s
m
[
0
1
-
5
.
0
1
T
]
s
m
[
0
5
0
4
0
2
T
]
s
m
[
-
-
0
0
5
3
T
]
s
m
[
-
-
0
0
3
4
T
]
s
m
[
-
0
0
5
1
0
4
5
T
]
s
m
[
-
-
-
6
T
]
s
m
[
-
-
0
0
0
1
7
T
0V
T2
T3
T4
T5
T7
LVDS Signal
Backlight On
10%
90%
90%
10%
VALID
DATA
Note 1
Note 3
Note 2
Power Supply VDD
Note1: insert a white pattern 360ms
Note2: insert a black pattern
Note3 :insert a white pattern after valid data and last until VDD falls to 10%.
Note4 :when AC on/off, timing rule of logo power on/off is the same as above.
T1
T6
