I-bus/Phoenix stingray ii+, Руководство пользователя, Страница: 72 / 90

Chapter 4 - AWARD BIOS Setup
Stingray II+ User's Guide 4-38
BIOS Reference - POST Codes
Note:
EISA POST codes are typically output to port address 300h.
ISA POST codes are output to port address 80h.
POST
(hex)
Description
C0 1. Turn off OEM specific cache, shadow...
2. Initialize all the standard devices with default values
Standard devices include:
-DMA controller (8237)
-Programmable Interrupt Controller (8259)
-Programmable Interval Timer (8254)
-RTC chip
C1 Auto-detection of onboard DRAM & Cache
C3 1. Test system BIOS checksum
2. Test the first 256K DRAM
3. Expand the compressed codes into temporary DRAM
area including the compressed System BIOS & Option
ROMs
C5 Copy the BIOS from ROM into E0000-FFFFF shadow RAM
so that POST will go faster
01-02 Reserved
03 Initialize EISA registers (EISA BIOS only)
04 Reserved
05 1. Keyboard Controller Self-Test
2. Enable Keyboard Interface
06 Reserved
07 Verifies CMOS's basic R/W functionality
BE Program defaults values into chipset according to the
MODBINable Chipset
Default Table
09 1. Program the configuration register of Cyrix CPU
according to the MODBINable Cyrix Register Table
2. OEM specific cache initialization (if needed)
0A 1. Initialize the first 32 interrupt vectors with corresponding
Interrupt handlers
Initialize INT no from 33-120 with Dummy(Suprious)
Interrupt Handler
2. Issue CPUID instruction to identify CPU type
3. Early Power Management initialization (OEM specific)