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Hynix Semiconductor GMS90C320 40, Руководство пользователя

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Hynix Semiconductor GMS90C320 40 Скачать руководство пользователя страница 23

GMS90C320

OCT. 2000 Ver 1.2

19

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-
priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of
the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within
each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.

Table 8
Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags)

Vector

Vector Address

IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt

0003

H

000B

H

0013

H

001B

H

0023

H

002B

H

Table 9
Interrupt Priority-Within-Level

Interrupt Source

Priority

IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2

External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt

High

↓

Low

Содержание GMS90C320 40

Страница 1: ...HYNIX SEMICONDUCTOR INC 8 BIT SINGLE CHIP MICROCONTROLLERS GMS90C320 User s Manual Ver 1 2 GMS90C320 PCB 24...

Страница 2: ...ductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however Hynix semiconduc...

Страница 3: ...e Naming Structure H G MS90X320 Frequency Package Type Blank 24MHz Blank PL Q 40PDIP 44PLCC 44MQFP Enhanced ROM less version Operating Voltage C L Normal voltage Low voltage Hynix semiconductor MCU XX...

Страница 4: ...RAM size bytes Operating max Frequency MHz Package Type 4 25 5 5 GMS90C320 40 GMS90C320 PL40 GMS90C320 Q40 ROM less 256 40 40PDIP 44PLCC 44MQFP GMS90C320 50 GMS90C320 PL50 GMS90C320 Q50 ROM less 256...

Страница 5: ...bit Timers Counters Timer 2 with up down counter feature USART Six interrupt sources two priority levels Power saving Idle and power down mode 2 7Volt low voltage version available P DIP 40 P LCC 44...

Страница 6: ...P1 3 P1 2 P1 1 T2EX P1 0 T2 N C V CC P0 0 AD0 P0 1 AD1 P0 2 AD2 P0 3 AD3 WR P3 6 RD P3 7 XTAL2 XTAL1 V S S N C P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P1 5 P1 6 P1 7 RESET RxD P3 0 N C TxD P3 1 IN...

Страница 7: ...AD7 EA ALE PSEN P1 6 P1 7 RESET RxD P3 0 TxD P3 1 INT0 P3 2 INT1 P3 3 T0 P3 4 T1 P3 5 WR P3 6 RD P3 7 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 T2 P1 0 T2EX P1 1 P1 2 P1 3 P1 4 P1...

Страница 8: ...4 P1 3 P1 2 P1 1 T2EX P1 0 T2 N C V CC P0 0 AD0 P0 1 AD1 P0 2 AD2 P0 3 AD3 WR P3 6 RD P3 7 XTAL2 XTAL1 V SS N C P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P1 5 P1 6 P1 7 RESET RxD P3 0 N C TxD P3 1 IN...

Страница 9: ...GMS90C320 OCT 2000 Ver 1 2 5 Logic Symbol Port 0 XTAL1 XTAL2 RESET EA ALE PSEN 8 bit Digital I O Port 1 8 bit Digital I O Port 2 8 bit Digital I O Port 3 8 bit Digital I O VCC VSS...

Страница 10: ...internal pulls up resistors Port 3 also serves the special features of the 80C51 family as listed below 11 10 5 P3 0 RxD receiver data input asynchronous or data input output synchronous of the serial...

Страница 11: ...esistor to VSS permits power on reset using only an external capacitor to VCC ALE 33 30 27 O The Address Latch Enable Output pulse for latching the low byte of the address during an access to external...

Страница 12: ...racteristics of the standard 80C32 the GMS90C320 incorporates some enhancements in the Timer 2 unit Figure 1 shows a block diagram of the GMS90C320 Figure 1 Block Diagram of the GMS90C320 RAM 256 x 8...

Страница 13: ...1 0 s Special Function Register PSW Reset value of PSW is 00H Bit Function CY Carry Flag AC Auxiliary Carry Flag for BCD operation F0 General Purpose Flag RS1 0 0 1 1 RS0 0 1 0 1 Register Bank select...

Страница 14: ...cial Function Register FFH 07H 00H 00H XXH2 XXH2 XXH2 0XXX0000B2 2 X means that the value is indeterminate and the location is reserved A0H A1H A2H A3H A4H A5H A6H A7H P21 reserved reserved reserved r...

Страница 15: ...H EEH EFH reserved reserved reserved reserved reserved reserved reserved reserved XXH 2 XXH 2 XXH2 XXH 2 XXH2 XXH 2 XXH 2 XXH2 D0H D1H D2H D3H D4H D5H D6H D7H PSW1 reserved reserved reserved reserved...

Страница 16: ...Port 1 Port 2 Port 3 80H 1 90H 1 A0H 1 B0H1 FFH FFH FFH FFH Serial Channels PCON SBUF SCON Power Control Register Serial Channel Buffer Register Serial Channel 0 Control Register 87H 99H 98H 1 0XXX000...

Страница 17: ...IDLE 88H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD GATE C T M1 M0 GATE C T M1 M0 8AH TL0 8BH TL1 8CH TH0 8DH TH1 90H P1 98H SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 99H SBUF A0H P2 A8H IE EA ET2 ES ET1...

Страница 18: ...FRs in Numeric Order cont d Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CAH RC2L CBH RC2H CCH TL2 CDH TH2 D0H PSW CY AC F0 RS1 RS0 OV F1 P E0H ACC F0H B SFR bit and byte addressab...

Страница 19: ...med to function as a gate to facilitate pulse width measurements Figure 2 illustrates the input clock logic Figure 2 Timer Counter 0 and 1 Input Clock Logic Table 4 Timer Counter 0 and 1 Operating Mod...

Страница 20: ...2CON EXEN P1 1 T2EX Remarks Input Clock RxCLK or TxCLK CP RL2 TR2 Internal External P1 0 T2 16 bit Auto reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 X X X 0 1 reload upon overflow reload trigger falling...

Страница 21: ...t clock 8 bit are transmitted received LSB first 1 0 1 Timer 1 2 overflow rate 8 bit UART 10 bits are transmitted through TxD or received RxD 2 1 0 or 9 bit UART 11 bits are transmitted through TxD or...

Страница 22: ...d control flags Figure 3 Interrupt Request Sources PT0 IP 1 High Priority Low Priority EA IE 7 TF0 TCON 5 Timer 0 Overflow TF1 TCON 7 IE0 TCON 1 IE1 TCON 3 TF2 T2CON 7 EXF2 T2CON 6 RI SCON 0 TI SCON 1...

Страница 23: ...t is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9 Table 8 Interrupt Sources and their Corresponding Interrupt Ve...

Страница 24: ...is restored to its normal operating level before the Power Down mode is terminated The reset signal that terminates the Power Down Mode also restarts the oscillator The reset should not be activated...

Страница 25: ...on 100 mA Power dissipation TBD Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the de...

Страница 26: ...LE PSEN VOL1 0 3 0 45 1 0 V IOL 200 A IOL 3 2mA1 IOL 7 0mA Output high voltage ports 1 2 3 VOH 2 4 0 9VCC V IOH 80 A IOH 10 A Output high voltage port 0 in external bus mode ALE PSEN VOH1 2 4 0 9VCC V...

Страница 27: ...9VCC specification when the address lines are stabilizing 3 ICC max at other frequencies is given by active mode ICC 1 0 OSC 3 16 idle mode ICC 0 37 OSC 3 63 where OSC is the oscillator frequency in...

Страница 28: ...high voltage ports 1 2 3 VOH 2 0 0 9VCC V IOH 20 A IOH 10 A Output high voltage port 0 in external bus mode ALE PSEN VOH1 2 0 0 9VCC V IOH 800 A2 IOH 80 A2 Logic 0 input current ports 1 2 3 IIL 1 50 A...

Страница 29: ...name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address C Clock D Input Data H Logic level HIGH I Instruction program mem...

Страница 30: ...n Max ALE pulse width tLHLL 127 2tCLCL 40 ns Address setup to ALE tAVLL 43 tCLCL 40 ns Address hold after ALE tLLAX 43 tCLCL 40 ns ALE low to valid instruction in tLLIV 233 4tCLCL 100 ns ALE to PSEN t...

Страница 31: ...E to valid data in tLLDV 517 8tCLCL 150 ns Address to valid data in tAVDV 585 9tCLCL 165 ns ALE to WR or RD tLLW L 200 300 3tCLCL 50 3tCLCL 50 ns Address valid to WR or RD tAVW L 203 4tCLCL 130 ns WR...

Страница 32: ...in Max ALE pulse width tLHLL 85 2tCLCL 40 ns Address setup to ALE tAVLL 23 tCLCL 40 ns Address hold after ALE tLLAX 43 tCLCL 40 ns ALE low to valid instruction in tLLIV 150 4tCLCL 100 ns ALE to PSEN t...

Страница 33: ...Z 75 2tCLCL 50 ns ALE to valid data in tLLDV 350 8tCLCL 150 ns Address to valid data in tAVDV 398 9tCLCL 165 ns ALE to WR or RD tLLW L 138 238 3tCLCL 50 3tCLCL 50 ns Address valid to WR or RD tAVW L 1...

Страница 34: ...x Min Max ALE pulse width tLHLL 43 2tCLCL 40 ns Address setup to ALE tAVLL 17 tCLCL 25 ns Address hold after ALE tLLAX 17 tCLCL 25 ns ALE low to valid instruction in tLLIV 80 4tCLCL 87 ns ALE to PSEN...

Страница 35: ...2tCLCL 20 ns ALE to valid data in tLLDV 200 8tCLCL 133 ns Address to valid data in tAVDV 220 9tCLCL 155 ns ALE to WR or RD tLLW L 75 175 3tCLCL 50 3tCLCL 50 ns Address valid to WR or RD tAVW L 67 4tC...

Страница 36: ...after ALE tLLAX 10 tCLCL 15 ns ALE low to valid instruction in tLLIV 55 4tCLCL 45 ns ALE to PSEN tLLPL 10 tCLCL 15 ns PSEN pulse width tPLPH 60 3tCLCL 15 ns PSEN to valid instruction in tPLIV 25 3tCLC...

Страница 37: ...38 2tCLCL 12 ns ALE to valid data in tLLDV 150 8tCLCL 50 ns Address to valid data in tAVDV 150 9tCLCL 75 ns ALE to WR or RD tLLW L 60 90 3tCLCL 15 3tCLCL 15 ns Address valid to WR or RD tAVW L 70 4tC...

Страница 38: ...CLCL 15 ns Address hold after ALE tLLAX 5 tCLCL 15 ns ALE low to valid instruction in tLLIV 40 4tCLCL 40 ns ALE to PSEN tLLPL 5 tCLCL 15 ns PSEN pulse width tPLPH 45 3tCLCL 15 ns PSEN to valid instruc...

Страница 39: ...28 2tCLCL 12 ns ALE to valid data in tLLDV 120 8tCLCL 40 ns Address to valid data in tAVDV 125 9tCLCL 55 ns ALE to WR or RD tLLW L 45 75 3tCLCL 15 3tCLCL 15 ns Address valid to WR or RD tAVW L 50 4tC...

Страница 40: ...S90C320 36 OCT 2000 Ver 1 2 Figure 4 External Program Memory Read Cycle tLHLL tPXAV tPXIZ tPXIX tLLAX tLLIV tPLIV tPLPH tAZPL tLLPL tAVLL A0 A7 INSTR IN A0 A7 A8 A15 A8 A15 tAVIV ALE PSEN PORT 0 PORT...

Страница 41: ...A15 from PCH ALE PSEN PORT 0 PORT 2 RD tLLWL DATA IN A0 A7 from PCL INSTR IN A0 A7 from tLLAX2 tAVWL tAVLL tAVDV tRLAZ tLLDV tRLRH tRLDV tRHDX tRHDZ tWHLH RI or DPL tLHLL P2 0 P2 7 or A8 A15 from DPH...

Страница 42: ...Test Points VCC 0 5V 0 45V Timing measurements are made a VIHmin for a logic 1 and VILmax for a logic 0 VLOAD 0 1 VLOAD 0 1 Timing Reference Points 0 2VCC 0 1 VOH 0 1 VOL 0 1 VLOAD For timing purpose...

Страница 43: ...uld consult the crystal manufacturer for appropriate values of external components XTAL2 P LCC 44 Pin 20 P DIP 40 Pin 18 M QFP 44 Pin 14 XTAL1 P LCC 44 Pin 21 P DIP 40 Pin 19 M QFP 44 Pin 15 CRYSTAL O...

Страница 44: ...0 Ver 1 2 Plastic Package P LCC 44 Plastic Leaded Chip Carrier 0 180 0 165 UNIT INCH 44PLCC 0 012 0 0075 0 120 0 090 0 032 0 026 0 630 0 590 min 0 020 0 656 0 650 0 695 0 685 0 656 0 650 0 695 0 685 0...

Страница 45: ...0 OCT 2000 Ver 1 2 41 Plastic Package P DIP 40 Plastic Dual in Line Package UNIT INCH 2 075 2 045 0 200 max 0 022 0 015 0 065 0 045 0 100 BSC 0 550 0 530 0 600 BSC 0 15 0 012 0 008 40DIP 0 140 0 120 m...

Страница 46: ...Plastic Package P MQFP 44 Plastic Metric Quad Flat Package 2 35 max SEE DETAIL A 1 03 0 73 0 7 0 25 0 10 1 60 REF DETAIL A UNIT MM 0 45 0 30 0 80 BSC 2 10 1 95 P MQFP 44 0 1 3 0 2 3 10 10 9 90 13 45...

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