Quidway® NetEngine 40E Core Router Switch and Route Processing Unit
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Out-band communication path among the boards of the entire system
The SRU board integrates the LAN Switch module to provide inter-board out-band
communication for various boards. It completes control, maintenance and message exchange
among the SRU, SFU and Line Processing Unit (LPU).
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Equipment management and maintenance function
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Data configuration function
The system configuration data, boot file, charging information, upgrade software and system
operation log are all saved on the SRU board. The SRU board provides a CF card interface as
a mass storage device to save data files.
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Reliability guarantee
In view of reliability, the 1+1 redundant backup mode is adopted for the MPUs. The MPUs
monitor each other’s status. Once the active MPU is faulty, the standby MPU automatically
becomes active.
2. Component of the system switching network
Two SFU modules integrated on the SRU and two SFU boards together form four switching planes
that implement 3+1 load sharing.
3. System clock unit
The SRU board provides Synchronous Digital Hierarchy (SDH) interface clock signals of high
precision and high reliability to various line boards. It provides two 2.048MHz synchronous clock
signals to the downstream equipment and may receive external 2.048MHz or 2.048Mbps reference
clock.
4. Switching synchronous clock unit
It ensures the synchronization of the working clocks of the switching network and various line
boards.
5. System maintenance unit
This board collects the operating data of various system units via the monitoring bus, and
generates control information according to the operating states of these units. Such control
information concerns board in-position detection, switching network operating status control, fan
speeding up, and so on. The 1+1 hot backup mode is adopted for the MPU, clock and LAN Switch
modules of the board, which raises the system reliability.
Specifications
Currently, the NE40E provides one type of SRU: CR52-SRUA. The CR52-SRUA board provides
multiple external interfaces. Its specifications and functions are described in the following table:
