l
Performs reverse power detection.
l
Synthesizes frequencies and tests loops.
l
Generates the CPRI clock, recovers the CPRI clock from loss of synchronization, and
detects alarms.
In addition, the DRFU of 900 MHz can be equipped with the Frequency Domain Reflectometer
(FDR) to implement the accurate VSWR test.
The modules inside the DRFU consist of the high-speed interface unit, signal processing unit,
power amplifier, and dual-duplexer unit.
shows the logical structure of the DRFU.
Figure 4-35
Logical structure of the DRFU
The high-speed interface unit performs the following functions:
l
Adapts and transfers the signals from the BBU to the signal processing unit.
l
Adapts and transfers the signals from the signal processing unit to the BBU.
The signal processing unit consists of two uplink RX channels and two downlink TX channels.
l
The uplink RX channels perform the following functions:
–
Down-converts the received RF signals to Intermediate Frequency (IF) signals.
–
Amplifies the IF signals and performs IQ modulation.
–
Performs analog-to-digital (A/D) conversion through the ADC.
–
Performs digital sampling.
–
Performs matched filtering.
–
Performs Digital Automatic Gain Control (DAGC).
–
Encapsulates the data.
l
The downlink TX channels perform the following functions:
–
Processes the signals (timing signals, control signals, and data signals) from the BBU
and sends them to the associated units.
–
Shapes and filters downlink signals.
–
Performs digital-to-analog (D/A) conversion through the DAC and performs IQ
modulation.
–
Up-converts RF signals to the TX band.
The PA amplifies the low-power RF signals that are received from the signal processing unit.
The dual-duplexer unit performs the following functions:
4 BTS3900 Components
BTS3900
Hardware Description
4-46
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Issue 04 (2011-02-15)